System and method for evaluating an integrated circuit design

Details System and method for evaluating an integrated circuit design System and method for evaluating an integrated circuit design

2005-09-13

2005-09-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S014000, C703S015000, C703S016000, C324S210000, C324S211000, C714S724000

Reexamination Certificate

active

06944837

ABSTRACT:
A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

REFERENCES:
patent: 6197605 (2001-03-01), Simunic et al.
patent: 6199031 (2001-03-01), Challier et al.
patent: 6370675 (2002-04-01), Matsumura et al.
patent: 6421634 (2002-07-01), Dearth et al.
patent: 6549881 (2003-04-01), Dearth et al.
patent: 2003/0237062 (2003-12-01), Whitehill

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