System and method for error correction in cache units

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Reexamination Certificate

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08065555

ABSTRACT:
A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.

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patent: 2002/0199151 (2002-12-01), Zuraski, Jr.
patent: 2007/0101238 (2007-05-01), Resnick et al.

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