Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-07-24
2011-10-04
Elmore, Reba I (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S159000
Reexamination Certificate
active
08032710
ABSTRACT:
A method and system of ensuring coherency of a sequence of instructions to be executed by a processor having a trace unit and an execution unit includes grouping at least a portion of the sequence of instructions to form at least one trace where a status of the at least one trace is set to a verified status when the at least one trace is formed; holding in the at least one trace a coherency component that includes a pointer to a physical address of the at least one trace; receiving, based on the coherency component, the pointer to the physical address as associated with an invalidating event, and in response thereto, setting the status of the at least one trace to be an unverified status; and preventing the at least one trace from being executed when the status of the at least one trace is the unverified status.
REFERENCES:
patent: 4912707 (1990-03-01), Kogge et al.
patent: 5369757 (1994-11-01), Spiro et al.
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5428786 (1995-06-01), Sites
patent: 5432918 (1995-07-01), Stamm
patent: 5491793 (1996-02-01), Somasundaram et al.
patent: 5568380 (1996-10-01), Brodnax et al.
patent: 5632023 (1997-05-01), White et al.
patent: 5644742 (1997-07-01), Shen et al.
patent: 5649136 (1997-07-01), Shen et al.
patent: 5673408 (1997-09-01), Shebanow et al.
patent: 5793947 (1998-08-01), Sakamoto
patent: 5838943 (1998-11-01), Ramagopal et al.
patent: 5860104 (1999-01-01), Witt et al.
patent: 5913925 (1999-06-01), Kahle et al.
patent: 5944841 (1999-08-01), Christie
patent: 5960198 (1999-09-01), Roediger et al.
patent: 6014742 (2000-01-01), Krick et al.
patent: 6018786 (2000-01-01), Krick et al.
patent: 6031992 (2000-02-01), Cmelik et al.
patent: 6052769 (2000-04-01), Huff et al.
patent: 6055630 (2000-04-01), D'Sa et al.
patent: 6073213 (2000-06-01), Peled et al.
patent: 6076144 (2000-06-01), Peled et al.
patent: 6115809 (2000-09-01), Mattson, Jr. et al.
patent: 6170038 (2001-01-01), Krick et al.
patent: 6170040 (2001-01-01), Lee et al.
patent: 6185660 (2001-02-01), Mulla et al.
patent: 6185675 (2001-02-01), Kranich et al.
patent: 6189141 (2001-02-01), Benitez et al.
patent: 6205545 (2001-03-01), Shah et al.
patent: 6216206 (2001-04-01), Peled et al.
patent: 6339822 (2002-01-01), Miller
patent: 6351844 (2002-02-01), Bala
patent: 6389446 (2002-05-01), Torii
patent: 6442674 (2002-08-01), Lee et al.
patent: 6449714 (2002-09-01), Sinharoy
patent: 6493837 (2002-12-01), Pang et al.
patent: 6538997 (2003-03-01), Wang et al.
patent: 6557095 (2003-04-01), Henstrom
patent: 6604060 (2003-08-01), Ryan et al.
patent: 6609189 (2003-08-01), Kuszmaul et al.
patent: 6671766 (2003-12-01), Vandenbergh et al.
patent: 6675376 (2004-01-01), Ronen et al.
patent: 6694427 (2004-02-01), Mericas et al.
patent: 6694457 (2004-02-01), McKee
patent: 6738926 (2004-05-01), Mathiske et al.
patent: 6779087 (2004-08-01), Saulsbury et al.
patent: 6785890 (2004-08-01), Kalafatis et al.
patent: 6799263 (2004-09-01), Morris et al.
patent: 6826182 (2004-11-01), Parthasarathy
patent: 6857060 (2005-02-01), Elias et al.
patent: 6874138 (2005-03-01), Ziegler et al.
patent: 6889318 (2005-05-01), Wichman
patent: 6895460 (2005-05-01), Desoli et al.
patent: 6950924 (2005-09-01), Miller et al.
patent: 6968476 (2005-11-01), Barowski et al.
patent: 6981104 (2005-12-01), Prabhu
patent: 6988190 (2006-01-01), Park
patent: 7003629 (2006-02-01), Alsup
patent: 7010648 (2006-03-01), Kadambi et al.
patent: 7062631 (2006-06-01), Klaiber et al.
patent: 7085955 (2006-08-01), Prabhu
patent: 7133969 (2006-11-01), Alsup et al.
patent: 7136922 (2006-11-01), Maiyuran et al.
patent: 7136992 (2006-11-01), Maiyuran et al.
patent: 7139902 (2006-11-01), Lee
patent: 7188368 (2007-03-01), Swimmer et al.
patent: 7213126 (2007-05-01), Smaus et al.
patent: 7269706 (2007-09-01), Agarwal et al.
patent: 7360024 (2008-04-01), Hironaka et al.
patent: 7366875 (2008-04-01), Rasche et al.
patent: 7415598 (2008-08-01), Dos Remedios
patent: 7487341 (2009-02-01), Wang et al.
patent: 7496735 (2009-02-01), Yourst et al.
patent: 7516366 (2009-04-01), Lev et al.
patent: 7536591 (2009-05-01), Varadarajan et al.
patent: 7546420 (2009-06-01), Shar et al.
patent: 7568089 (2009-07-01), Favor et al.
patent: 7571304 (2009-08-01), Chaudhry et al.
patent: 7577690 (2009-08-01), Chandrasekaran et al.
patent: 7594111 (2009-09-01), Kiriansky et al.
patent: 7600221 (2009-10-01), Rangachari
patent: 7606975 (2009-10-01), Shar et al.
patent: 2001/0032307 (2001-10-01), Rohlman et al.
patent: 2002/0013938 (2002-01-01), Duesterwald et al.
patent: 2002/0095553 (2002-07-01), Mendelson et al.
patent: 2002/0144101 (2002-10-01), Wang et al.
patent: 2002/0147890 (2002-10-01), Saulsbury et al.
patent: 2003/0005271 (2003-01-01), Hsu et al.
patent: 2003/0009620 (2003-01-01), Solomon et al.
patent: 2003/0084375 (2003-05-01), Moore et al.
patent: 2004/0015627 (2004-01-01), Desoli et al.
patent: 2004/0034757 (2004-02-01), Gochman et al.
patent: 2004/0083352 (2004-04-01), Lee
patent: 2004/0107336 (2004-06-01), Douglas et al.
patent: 2004/0154011 (2004-08-01), Wang et al.
patent: 2004/0193857 (2004-09-01), Miller et al.
patent: 2004/0230778 (2004-11-01), Chou et al.
patent: 2005/0012079 (2005-01-01), Roberts et al.
patent: 2005/0097110 (2005-05-01), Nishanov et al.
patent: 2005/0108719 (2005-05-01), Need et al.
patent: 2005/0120179 (2005-06-01), Akkary et al.
patent: 2005/0125632 (2005-06-01), Alsup et al.
patent: 2005/0289324 (2005-12-01), Miller et al.
patent: 2005/0289529 (2005-12-01), Almog et al.
patent: 2006/0053245 (2006-03-01), Solomon et al.
patent: 2006/0053347 (2006-03-01), van Ingen et al.
patent: 2006/0080190 (2006-04-01), Furukawa et al.
patent: 2006/0179346 (2006-08-01), Bishop et al.
patent: 2006/0184771 (2006-08-01), Floyd et al.
patent: 2007/0038844 (2007-02-01), Valentine et al.
patent: 2007/0157007 (2007-07-01), Jourdan et al.
patent: 2008/0034350 (2008-02-01), Conti
patent: 2009/0222596 (2009-09-01), Flynn et al.
patent: 2010/0031000 (2010-02-01), Flynn et al.
Patel, S., Lumetta, S., “rePlay: A Hardware Framework for Dynamic Optimization”, IEEE Transactions on Computers, vol. 50, No. 6, Jun. 2001 (19 pages).
Tanenbaum, A.S., “Structured Computer Organization”, Prentice-Hall, 2nd Edition, 1984, p. 11 (1 page).
Patel S. J. et al., Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing, IEEE, 1998, pp. 262-271.
Tanenbaum, A. S., Structured Computer Organization, Second Edition, Prentice Hall, Inc. 1984, pp. 10-12.
Almog, Y. et al., Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture, Proceedings of the International Symposium on Code Generation and Optimization, 2004 (12 pages).
Chaparro, P. et al., Distributing the Fronted for Temperature Reduction, Proceedings of the 11th Symposium on High-Performace Computer Architecture, Feb. 12-16, 2005 (10 pages).
Colwell, R. P. et al., A VLIW Architecture for a Trace Scheduling Compiler, 1987, pp. 180-192 (13 pages).
Fisher, J. A., Trace Scheduling: A Technique for Global Microcode Compaction, IEEE Transactions on Computers, vol. C-30, No. 7, Jul. 1981, pp. 478-490 (13 pages).
Friendly, D. et al, Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors, Proceedings of the 31st Annual ACM/IEEE International Symposium on Microacrhictecture, Nov. 30-Dec. 2, 1998, pp. 173-181 (9 pages).
Grunwald, D. and Ghiasi, S., Microarchitectural Denial of Service: Insuring Microarchitectural Fairness, Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 18-22, 2002 (10 pages).
Hinton, G. et al., The Microarchitecture of the Pentium 4 Processor, Intel Technology Journal Q1, 2001 (12 pages).
IBM Technical Disclosure Bulletin, Grouping of Instructions, v. 38, n. 8, Aug. 1, 1995, pp. 531-534 (4 pages).
Katevenis, E. G., Reduced Instruction Set Computer Architectures for VLSI, Berkley, California 1983, pp. 67-68 and 190 (7 pages).
Rotenberg, E., Bennett, S., and Smith, J. E., Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching, In Proceedings of the 29th Annual Inter
Ashcraft Matthew
Favor John Gregory
Rowlands Joseph
Shar Leonard E.
Thaik Richard
Elmore Reba I
Oracle America Inc.
Osha • Liang LLP
LandOfFree
System and method for ensuring coherency in trace execution does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for ensuring coherency in trace execution, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for ensuring coherency in trace execution will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4279426