Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-10-15
1999-02-16
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
36518518, G06F 1200
Patent
active
058731121
ABSTRACT:
A method and system in which X-bit packets of bits (where X is an integer) are encoded to generate X-bit packets of encoded bits for writing to erased cells of a flash memory array, where less power is consumed to write a bit having a first value to an erased cell than to write a bit having a second value to the cell. Preferably, a count signal is generated for each packet of raw bits indicating the number of bits of the packet having the first (or second) value, the count signal is processed to generate a control signal which determines an encoding for the packet, and the raw bits of the packet are encoded according to a scheme determined by the control signal. In some embodiments, each erased cell is indicative of the binary value "1", the count signal is compared to a reference value (indicative of X/2) to generate a control signal determining whether the packet should undergo polarity inversion, and the packet is inverted (or not inverted) depending on the value of the control signal. In alternative embodiments, a count signal is generated for each packet of bits to be written to erased cells of an array (where the count signal indicates the number of bits in the packet having a particular value), and each packet is encoded in a manner determined by the corresponding count signal to reduce the power needed to write the encoded bits to the erased cells. Preferably, flag bits indicative of the encoding of each packet are generated, and the flag bits (as well as the encoded packets) are stored in cells of the flash memory array.
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Langjahr David
Micro)n Technology, Inc.
Swann Tod R.
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