Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2000-09-29
2004-12-21
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S223000, C712S224000, C712S300000, C708S490000, C710S066000, C710S307000
Reexamination Certificate
active
06834337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to systems and methods for processing data in computer registers.
2. Description of the Related Art
Computer processors function by processing data elements through various registers in accordance with instructions provided by a computer program. The registers have a capacity that is a power of two. For instance, a register might have a capacity of 8 bits, and it would be able to process, in a single processing cycle, a data element having up to eight bits in the element. As an example, an 8-bit register can process a 4-bit data element in a single cycle. Of course, registers typically have sizes larger than 8 bits, i.e., registers can have 16 bit capacities, or 32 bits, or 64 bits, and so on. Non-limiting illustrative examples of the types of operations undertaken by registers include multiplication by a constant, addition, subtraction, shift-left-logical, shift-right-logical, AND, and OR operations.
After the data elements have been processed, they can be sent to another register for further processing, or they can be stored or output. To illustrate, in the printer field a server microprocessor processes an input data stream through its various registers in accordance with a computer program, and it might output a data stream of compressed image data in so-called JPEG format to a printer processor, which then operates on the data as appropriate to instruct a printer apparatus how to print the image.
The processor itself executes instructions in the form of machine language, which are the lowlevel instructions relating to what data elements are processed through which registers. Most software, however, is written in higher-level programming code such as C, which has the advantages of being human readable and of embodying relatively complex processing operations using comparatively short, quickly-written commands. A compiler receives the high-level programming code, decides the best way among many choices to map it into assembly language, passes the mapping to an assembler, and the assembler then maps the assembly language into so-called machine language that is readable by a processor. From time to time, a programmer may elect to write parts of the program that are executed more frequently than other parts directly in a lower-level language. While more cumbersome to write, these so-called “hand-crafted” portions of code do not have to be translated by a high level language compiler and, thus, facilitate faster processing at run time.
Regardless of whether the processor receives the machine code from a compiler or directly from a hand-crafted program, however, the present invention makes the critical observation that it is often the case that register space is wasted. More particularly, as intimated above, a register might not be used to its full capacity in every processing cycle. For instance, when a 16-bit capacity register is used to process 4-bit data elements, 12 bits of the register per cycle are wasted. This slows processing time, creates additional data caching requirements (and attendant cache miss problems), and in general fails to fully exploit processor capacity. Accordingly, the present invention recognizes the potential improvement in processor performance that would inure were multiple data elements to be processed in a register in a single cycle.
The present invention further understands that implementing the above recognition is not trivial, particularly if both positive and negative (that is, “signed”) values, and not just positive values, are to be processed, owing to the possibility of exceeding register capacity and/or corrupting data during processing. Stated differently, as used by the present invention a “signed” data element is one that is not constrained to be non-negative, and it is desirable that multiple signed data elements be processed through a single register in a single processing cycle. Furthermore, the present invention understands that for robustness, it is desirable that a processor not be constrained by the manufacturer to accept multiple data elements per register of only predetermined bit sizes, but rather that a programmer have the flexibility to define various data element bit sizes that can be accepted by a register as the particular application might happen to dictate. Having made the above-noted observations, the present invention provides the solutions disclosed herein.
SUMMARY OF THE INVENTION
A general purpose computer is programmed according to the inventive steps herein to enable the use of more than one multi-bit, signed data element in a single register. The invention can also be embodied as an article of manufacture—a machine component—that is used by a digital processing apparatus such as a computer and which tangibly embodies a program of instructions that are executable by the digital processing apparatus to execute the present logic. This invention is realized in a critical machine component that causes a digital processing apparatus to perform the inventive method steps herein.
Accordingly, a general purpose computer includes logic for undertaking method acts to establish at least first and second signed, multi-bit data elements in at least a first register. The logic simultaneously processes the multiple elements.
If desired, the elements can be independent of each other. The first element can be provided from a first data set and the second element can be provided from a second data set, or both elements can be provided from different parts of the same data set. The register itself can pass contents to computational subsystems including but not limited to adders, or multipliers, or shifters, and the operation performed on the data elements simultaneously can be, but is not limited to, a multiplication by a constant or by a variable of known precision, or an addition, or a shift-left logical.
Further, larger data elements can be split among registers and then recombined after processing. That is, the first element can be a first partial element having a related second partial element established in a second register, and the first and second partial elements are combined after processing.
As set forth further below, a respective precision is allocated in a register for each data element to be processed in the register during a single cycle such that the maximum negative number that can be represented by a data element is one larger than the maximum negative number that can be represented in the respective precision. This can include determining a precision bound for a data element based on [−2
N−1+
1] to [+2
N−1
1 ], wherein N is the number of bits in the data element.
Additionally, in a preferred embodiment and prior to execution the logic determines a net number of bits required for any multiplicative constants to achieve a desired precision. Then, using the net number of bits and multiplicative constant, a net number of bits of precision is determined. Space in the register is allocated in accordance with precision determinations.
Once the registers have been set up by allocating space for multiple signed data elements per register, processing of the data elements is executed by packing multiple data elements into individual registers according to the net number of bits of precision. All data elements in each register are then simultaneously operated on using the same operand. The data elements are then passed on for further processing, storage, or output.
When first and second data elements in a register are to be made independent of each other, the logic adds a sign bit in the first element to the least significant bit in the second element. Alternatively, the method embodied by the logic then includes masking sign bits in the first and second elements, adding the sign bits back in to the register, and discarding the value in the position of the sign bits in each element.
Moreover, it can be determined whether a data element is contained around zero as set forth further below. Also
Brady Michael Thomas
Mitchell Joan Laverne
Trelewicz Jennifer Q.
International Business Machines - Corporation
Pan Daniel H.
Roitz John L.
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