Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-12
2008-11-04
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S120000, C430S005000, C378S035000
Reexamination Certificate
active
07448018
ABSTRACT:
A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.
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Heng Fook-Luen
Lavin Mark Alan
Lee Jin-Fuw
Lin Chieh-yu
Nayak Jawahar Pundalik
International Business Machines - Corporation
Keusey, Tutunjian & & Bitetto, P.C.
Kik Phallaka
Verminski, Esq. Brian P.
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