Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2001-11-08
2002-10-22
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S264000, C327S284000, C327S288000
Reexamination Certificate
active
06469559
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of systems and methods for eliminating pulse width variations in digital delay lines. More particularly, the present invention relates to a system and method for ensuring the accurate preservation of the width of pulses propagated through relatively long delay voltage controlled delay lines of particular utility in conjunction with delay locked loops (“DLL”) such as those utilized in double data rate (“DDR”) dynamic random access memory (“DRAM”) devices, processors and other integrated circuit (“IC”) devices and semiconductor processes.
One particular application of relatively long delay voltage controlled delay lines is in conjunction with DDR DRAMs. Currently, these memory ICs are able to achieve an effective doubling of the device's bandwidth by inclusion of DLL circuitry to achieve synchronization of data accesses at a point in time to enable the reading of data on both the rising and falling edges of each clock cycle. In such DLL circuits, a phase detector is utilized to determine the relative phase between two clock signals, such as the system clock and synchronization (“sync”) clock signals. In any event, the DLL is operational to adjust one or more control voltages applied to a voltage controlled delay line until the two clock signals are perfectly in phase.
In order to delay a digital pulse or stream of pulses in such a DLL circuit, a string of an even number of series coupled inverters is often used. If it is desired to make the delay variable, the inverters may include some means of adjusting the delay through the inverter with an applied external voltage level. If comparatively long delays are required, such as those often used in DLLs, the number of inverters in the chain can be relatively high, e.g. on the order of twenty or more.
In order for a pulse to propagate through the delay line without any change in pulse width, there are two possibilities: 1) the propagation delays for both the rising inputs and falling inputs must be made identical for each individual inverter; or 2) the delay for rising edge inputs are made identical on an odd-even basis and the delay for falling edge inputs are made identical on an odd-even basis. In this latter regard, an “odd-even” basis means inverter pairs 1 and 2, 3 and 4 etc. The former case is very difficult to achieve because of the variations in the pull-up or pull-down devices in the individual delay inverters. Consequently, it is easier to achieve the latter case, but it too requires that each odd-even pair of delay inverters be made identical and that the parasitic loading between all inverters also be the same. These restrictions are even more critical if voltage controlled delay inverters are used (as in DLL's) because of the added sensitivity to device parameters. For efficient layout of the delay line and to minimize sensitivity in an integrated circuit, it is most desirable to eliminate the requirement for everything to be matched at the individual inverter level.
SUMMARY OF THE INVENTION
In accordance with the system and method disclosed herein, a delay line is partitioned into two substantially identical blocks of delay inverters with a first inverter being inserted between the two blocks and a second substantially identical inverter at the output of the second block. In this manner, the requirement for matching at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. The layout of the delay inverters in a single block can be effectuated in the most efficient manner possible and the same identical layout can be used for the first and second blocks.
Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks. If the loading of the inverter at the output of the first block and that of the inverter at the output of the second block are identical, the pulse width will be perfectly preserved.
Particularly disclosed herein is delay line for delaying an input signal between input and output lines thereof, the delay line comprising first and second substantially identical blocks of delay elements, the first block of delay elements being coupled to receive the input signal on the input line; a first inverter coupled to an output of the first block of delay elements for providing an inverted delayed signal to the second block of delay elements; and a second substantially identical inverter coupled to an output of the second block of delay elements for providing a re-inverted delayed signal on the output line.
Also disclosed herein is a method for delaying a signal received on an input line and providing a delayed output signal on an output line. The method comprises the steps of: providing first and second substantially identical blocks of delay elements; coupling the first block of delay elements to receive the input signal on the input line; providing first and second substantially identical inverters; coupling the first inverter to an output of the first block of delay elements; providing an inverted delayed signal to the second block of delay elements at an output of the first inverter; receiving the inverted delay signal at an input of the second block of delay elements; and coupling the second inverter to an output of the second block of delay elements for providing the delayed signal on the output line.
REFERENCES:
patent: 4899071 (1990-02-01), Morales
patent: 5039893 (1991-08-01), Tomisawa
patent: 5231319 (1993-07-01), Crafts et al.
patent: 6147532 (2000-11-01), Ueda
patent: 6313681 (2001-11-01), Yoshikawa
A Low-Power CMOS Time-to-Digital Converter, IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Raisanen-Ruotsalainen et al., 9/95.
Clock Buffer Chip with Multiple Target Automatic Skew Compensation, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Watson, Jr. & Iknaian, 11/95.
A 64-Mbit, 640-MByte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mW DLL for a 256-MByte Memory System, IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Kim et al., 11/98.
The Delay Vernier Pattern Generation Technique, IEEE Journal of Solid-State Circuits, vol. 32, No. 4, Moyer et al. 4/97.
A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Combes et al., 7/96.
A 250-622 MHZ Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture, IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Tanoi, 4/96.
An Integrated High Resolution CMOS-Timing Generator Based on an Array of Delay Locked Loops, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Christainsen, 7/96.
A 800MB/s 72Mb SLDRAM with Digitally-Calibrated DLL, IEEE Journal of Solid-State Circuits Conference/Session 24/Paper WP24.3, Paris et al., 6/99.
Callahan Timothy P.
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
Mosel Vitelic Inc.
LandOfFree
System and method for eliminating pulse width variations in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for eliminating pulse width variations in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for eliminating pulse width variations in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2961403