Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-29
2001-07-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C326S089000, C326S124000, C327S382000, C327S391000
Reexamination Certificate
active
06266800
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The invention relates generally to a method and apparatus for measuring setup time in dynamic logic circuits. More specifically, the invention relates to a method and apparatus of measuring setup up time of SOI field effect transistors (FET) in dynamic logic circuits.
B. Description of Related Art
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
In recent years Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) integrated circuits and Complementary Metal Oxide Semiconductor (CMOS) FETs have gained popularity and are the most widely used type of integrated circuit technology. Today, CMOS electronic devices provide advantages of higher operating speeds, smaller size, lower power consumption, and are increasingly becoming cheaper to manufacture as a result of smaller component size, higher manufacturing production yields per semiconductor wafer, and larger wafer sizes. The most popular integrated circuit devices manufactured utilizing CMOS technology are microprocessors, memory, and digital logic circuits.
Traditional MOS and CMOS semiconductors consist of a metal on an oxide layer that is placed on a silicon substrate. The added impurities in the silicon substrate enable these devices to operate as transistors. On the other hand, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon oxide or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. Therefore, with SOI technology faster MOS transistors can be manufactured resulting in higher performance semiconductors to fuel emerging needs for faster electronic devices.
SOI technology has several drawbacks. An inherent drawback of placing a MOS transistor on top of a SOI layer is that the MOS transistor is actually placed in parallel with a bipolar junction transistor. If enough current is passed through the MOS transistor, the parasitic bipolar transistor will turn on. This causes an unwanted effect called bipolar discharge and lowers the performance of the MOS transistor.
High speed CMOS circuits often employ a domino circuit technique that utilizes pre-charging to improve the gate speeds of the transistors. Circuit nodes are pre-charged during each clock cycle to a certain level. The problem with SOI FETs is that the parasitic bipolar transistor causes bipolar discharge. This is undesirable because it causes an unintended loss of charge on the drain nodes of the dynamic circuit.
Normally, parasitic bipolar action does not manifest itself in conventional, bulk, MOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar off. In SOI, the body of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when the drain and source terminals of the MOS FET are at a high potential. Subsequently, if the source is pulled to a low potential, the trapped charge in the base area is available as parasitic base current. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET. The unintentional loss of charge could lead to system failure, for example, by erroneously switching logic state.
It will be appreciated by those skilled in the art that a technique for eliminating parasitic bipolar discharge in MOS FET devices can be provided as discussed in U.S. patent application Ser. No. 09/240,244, filed Jan. 29, 1999, and entitled “Method And Apparatus For Elimination Of Parasitic Bipolar Action In Complementary Oxide Semiconductor (CMOS) Silicon On Insulator (SOI) Circuits,” the disclosure of which is hereby incorporated herein by reference.
It will also be appreciated by those skilled in the art that a technique for eliminating parasitic bipolar discharge in logic circuits including CMOS SOI devices can be provided as discussed in U.S. patent application Ser. No. 09/239,991, filed Jan. 29, 1999 and entitled “Method And Apparatus For Elimination Of Parasitic Bipolar Action In Logic Circuits Including Complementary Oxide Semiconductor (CMOS) Silicon On Insulator (SOI) Elements,” the disclosure of which is also hereby incorporated herein by reference.
It will also be appreciated by those by those skilled in the art that yet another technique for eliminating parasitic bipolar discharge in logic circuits including CMOS SOI devices can be provided as discussed in U.S. patent application Ser. No. 09/239,289, filed Jan. 29, 1999 and entitled “Method And Apparatus For Elimination Of Parasitic Bipolar Action In Logic Circuits For History Removal Under Stack Contention Including Complementary Oxide Semiconductor (CMOS) Silicon On Insulator (SOI) Elements,” the disclosure of which is also hereby incorporated herein by reference.
Dynamic Logic circuits utilize a “setup” time for the various logic inputs. “Setup” time is generally defined as the time within which an input data signal should be provided to an input of a logic circuit to guarantee the stability of the logic circuit's output. It will be appreciated that the output of the logic circuit should be stable prior to a subsequent clock signal arriving at the clock input of a dynamic logic circuit. Accordingly, the output stability of the circuit cannot be guaranteed if the input signal does not arrive at the circuit's input prior to the clock signal. The time within which the input data signal must “beat” the clock signal is referred to as the “setup” time.
In CMOS Dynamic Logic circuits that do not employ SOI technology, “setup” is a delay time defined as the difference between the time required by the input data signal to propagate from the circuit data input to a point where it coincides with the clock signal; and the time required by the clock signal to propagate from the circuit clock input to a point where it coincides with the data input signal.
FIG. 3
is a schematic of a dynamic logic circuit illustrating a method for measuring data setup time that is well known in the art. Dynamic logic circuit
44
, within logic partition
46
, includes a clock signal input (CLK) and a data signal input (DATA). The DATA input is fed to an arbitrary logic circuit
56
(LOGIC). The DATA signal propagates from the DATA input of logic partition
46
to the gate input
52
(Test_Node) of negative field effect transistor (NFET)
62
.
The time delay along data signal path
48
, from the DATA signal input to the gate input
52
of NFET device
62
is D1. The time delay along clock signal path
50
, from the CLK signal input to the gate input
54
(LClk_e) of NFET evaluate device
60
is D2. The setup time, SETUP, for the dynamic circuit
44
is defined by the equation at TABLE 1 as the difference between time delays D1 and D2, along signal paths
48
and
50
, respectively, as:
TABLE 1
SETUP=D1−D2
However, those skilled in the art will appreciate that in dynamic logic circuits, timing tools such as PATHMILL and EINSTIMER (for example), measure the time delay D2 along clock signal path
50
to the gate input
54
of evaluate transistor
60
.
In CMOS Dynamic Logic circuits employing SOI technology, it is preferable that the time delay should be measured along the CLK signal to the gate input
66
(LClk_p) of precharging transistor
58
. I
Storino Salvatore N.
Uhlmann Gregory John
International Business Machines - Corporation
Merchant & Gould
Smith Matthew
Thompson A. M.
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