Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
1997-09-24
2001-03-20
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S108000, C710S108000, C710S104000, C710S120000, C714S014000, C307S075000, C307S098000, C257S355000
Reexamination Certificate
active
06205500
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system and method for electrically isolating a device from a conmnon bus, and more particularly to a method and apparatus for utilizing decode logic and a switching device to electrically isolate a device from higher voltage devices sharing a common bus.
DESCRIPTION OF THE RELATED ART
Many electronic devices, including computers systems and peripherals, are based on the conventional five volt transistor-transistor logic (TTL) standard. For example, many computer systems include one or more processors, support logic, controllers and memory devices coupled to a common bus, where all of the devices operate based on the 5 volt TTL standard. In this 5 volt environment, communication between the various devices sharing the common bus was not a problem since all of the components and devices were designed to operate at 5 volts. There has been a move toward power conservation, however, that has driven manufacturers to produce memory devices and processors that operate at lower voltage levels, such as 3.3 volts. In laptop computers, for example, power conservation is essential to prolong the life of rechargeable batteries. This is also true for many peripheral or expansion devices of larger computer systems, where it is desired to reduce power consumption to reduce the strain on the peripheral or expansion bus. In spite of the trend towards reducing energy consumption, many devices and components still operate at higher voltage levels to obtain necessary high performance levels. Higher voltage levels often allow faster logic transitions and corresponding reduced latency to improve timing and performance.
A hybrid system combining lower and higher voltage devices may present problems for computer system designers. Some devices are designed to operate at lower voltage logic levels but are tolerant to higher voltage levels. For example, several processor manufacturers have begun producing processors for all types of computer systems that operate at 3.3 volts, but are 5 volt tolerant. This allows both 5 and 3.3 volt devices to safely communicate with the processor over a common bus. Some devices, however, operate at lower voltage levels and are sensitive to higher voltage levels. For example, some 3.3 memory devices are not 5 volt tolerant and thus are not capable of operating on the same bus as 5 volt devices, since otherwise the higher voltage levels would destroy part or all of the memory. Thus, when a 5 volt device accesses the conmnon bus, the 3.3 volt memory device could be damaged because of the excessive power dissipation output onto the bus by the 5 volt devices,
Thus, the need exists for a way of isolating devices from a bus shared by higher voltage devices but still allowing the lower voltage devices to communicate with a lower voltage processor.
SUMMARY OF THE INVENTION
An isolation system and method according to the present invention electrically couples a device to a bus during access of that device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to a low voltage device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates said device from the bus. The isolation system flrther includes enable logic that detects cycles on the bus and provides the enable signal to the enable input of the isolation device during a cycle if the cycle is intended for the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus. Generally, the enable logic may comprise decode logic that decodes an address on the bus during an access cycle to determine if the address corresponds to an address of the lower voltage device. In an embodiment described herein, the low voltage device is a low voltage memory device that is coupled to the bus via the isolation device only during memory cycles executed on the bus to access the memory device.
The switching device may include a first set of contacts coupled to the bus and a second set of contacts coupled to corresponding signal contacts of the low voltage device. The switching device electrically isolates the low voltage device from the bus by electrically isolating its first set of contacts from its second sets of contacts. Upon receiving the enable signal, the switching device electrically couples the low voltage device to the bus. In particular, when the switching device receives the enable signal, it transitions from an open position, high impedance state to a closed, low impedance state, which directly couples signal lines of the bus to corresponding signal contacts of the low voltage device.
A processor is typically the device that executes cycles on the bus and asserts addresses corresponding to the low voltage device for accessing that device. The processor generally operates at the same low voltage as the low voltage device, but is tolerant to higher voltage levels of other devices on the bus. Thus, the processor may communicate with various other higher voltage devices coupled to the bus while the low voltage device is isolated. For a low voltage memory device, the processor generally executes either read or write cycles and asserts an address onto the bus corresponding to or associated with the memory device. Typically, the memory device has a predetermined set of addresses or an address range for addressing the memory. Decode logic coupled to the bus decodes an address asserted on the bus during a memory cycle to determine whether the address is within the predetermined address range of the memory device. The decode logic thus detects the memory cycle, decodes the address and asserts the enable signal to the switching device if the address indicates the memory device. In this manner, the processor reads data from or writes data to the memory device while coupled to the bus via the switching device.
During communication between the processor and the low voltage device, the other higher voltage devices coupled to the bus are either in a high impedance state or are otherwise isolated from the bus to electrically isolate the low voltage device from the higher voltage levels.
REFERENCES:
patent: 4481430 (1984-11-01), Houk et al.
patent: 4964011 (1990-10-01), Sternglass
patent: 5229652 (1993-07-01), Hough
patent: 5265211 (1993-11-01), Amini et al.
patent: 5301287 (1994-04-01), Herrel et al.
patent: 5317721 (1994-05-01), Robinson
patent: 5365181 (1994-11-01), Mair
patent: 5467453 (1995-11-01), Kocis
patent: 5493534 (1996-02-01), Mok
patent: 5546042 (1996-08-01), Tedrow et al.
patent: 5557758 (1996-09-01), Bland et al.
patent: 5559966 (1996-09-01), Cho et al.
patent: 5561384 (1996-10-01), Reents et al.
patent: 5563838 (1996-10-01), Mart et al.
patent: 5572663 (1996-11-01), Hosaka
patent: 5596708 (1997-01-01), Weber
patent: 5625593 (1997-04-01), Kimura
patent: 5636288 (1997-06-01), Bonneville et al.
patent: 5671179 (1997-09-01), Javanifard
patent: 5680063 (1997-10-01), Ludwig et al.
patent: 5796992 (1998-08-01), Reif et al.
patent: 5822512 (1998-10-01), Goodrum et al.
patent: 5822547 (1998-10-01), Boesch et al.
patent: 5828600 (1998-10-01), Kato et al.
patent: 5938751 (1999-08-01), Tavallaei et al.
patent: 5943482 (1999-08-01), Culley et al.
patent: 5945713 (1999-08-01), Voldman
patent: 674274A1 (1995-09-01), None
patent: 788058A1 (1997-08-01), None
European Search Report regarding Application No. 98307413.9 dated Aug. 1, 1999.
Grieff Thomas W.
Sabotta Michael L.
Akin Gump Strauss Hauer & Feld & LLP
Compaq Computer Corp.
Jean Frantz
Sheikh Ayaz R.
LandOfFree
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