System and method for efficiently testing a large random...

Details System and method for efficiently testing a large random... System and method for efficiently testing a large random...

2007-12-04

2007-12-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S733000

Reexamination Certificate

active

10646535

ABSTRACT:
A system for, and method of, allowing conventional memory test circuitry to test parallel memory arrays and an integrated circuit incorporating the system or the method. In one embodiment, the system includes: (1) bit pattern distribution circuitry that causes a probe bit pattern generated by the memory test circuitry to be written to each of the memory arrays, (2) a pseudo-memory, coupled to the bit pattern distribution circuitry, that receives a portion of the probe bit pattern and (3) combinatorial logic, coupled to the pseudo-memory, that employs the portion and data-out bit patterns read from the memory arrays to generate a response bit pattern that matches the probe bit pattern only if all of the data-out bit patterns match the probe bit pattern.

REFERENCES:
patent: 4433413 (1984-02-01), Fasang
patent: 5553082 (1996-09-01), Connor et al.
patent: 5612916 (1997-03-01), Neduva
patent: 5825782 (1998-10-01), Roohparvar

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