System and method for efficiently performing data transfer...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process

Reexamination Certificate

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Details

C710S018000, C710S052000, C712S225000

Reexamination Certificate

active

06678749

ABSTRACT:

BACKGROUND SECTION
1. Field of the Invention
This invention relates generally to techniques for managing data, and relates more particularly to a system and method for efficiently performing data transfer operations.
2. Description of the Background Art
Implementing efficient methods for transferring data is a significant consideration for designers and manufacturers of contemporary electronic devices. However, efficiently transferring data with electronic devices may create substantial challenges for system designers. For example, enhanced demands for increased device functionality and performance may require more system processing power and require additional hardware resources. An increase in processing or hardware requirements may also result in a corresponding detrimental economic impact due to increased production costs and operational inefficiencies.
Furthermore, enhanced device capability to perform various advanced transfer operations may provide additional benefits to a system user, but may also place increased demands on the control and management of various device components. For example, an enhanced electronic device that transfers digital image data may benefit from an effective implementation because of the large amount and complexity of the digital data involved.
In certain contemporary environments, complex or lengthy data transfer operations may often consume substantial amounts of available system resources to the detriment of other system functionalities. For example, a system central processing unit may operate at a faster rate than other device components. This disparity in operating speeds may make it difficult for the other device components to perform one or more data transfer operations at a speed that compliments the central processing unit and does not slow down the overall operations of the central processing unit and electronic system.
Due to growing demands on system resources and substantially increasing data magnitudes, it is apparent that developing new techniques for transferring data is a matter of concern for related electronic technologies. Therefore, for all the foregoing reasons, developing efficient systems for transferring data remains a significant consideration for designers, manufacturers, and users of contemporary electronic devices.
SUMMARY
In accordance with the present invention, an apparatus and method are disclosed for efficiently performing data transfer operations in an electronic system. In one embodiment, a central processing unit may preferably issue one or more commands to a central processing unit (CPU) interface. The CPU interface may temporarily store the one or more commands into a command buffer. The CPU interface may also temporarily store any data to be written to a device into a write buffer, and may store any data to be read from a device into a read buffer. The CPU interface may then issue each command from the command buffer to a peripheral or peripheral interface when the corresponding peripheral or peripheral interface is ready.
In another embodiment of the invention, one or more commands may be temporarily stored in a command buffer associated with a memory interface. The one or more commands may be received from the CPU interface, one or more peripheral interfaces, and one or more peripheral devices. When a command is executed, data corresponding to the command may be temporarily stored in one or more buffers associated with a receiving device. When the receiving device is ready, the data temporarily stored in the buffers may be transferred to the device.
In yet another embodiment of the present invention, a command count may be incremented in response to the issuance of a command. When each command is executed, the command count may be decremented. This provides the system with a command count of the number of outstanding commands that have yet to be executed.
The commands stored in the command buffers associated with the CPU interface and the memory interface may be executed in any appropriate order. The commands may be executed in a first-in-first-out order, or the commands may be prioritized and executed in a sequence that optimizes system operations.
In accordance with the present invention, the central processing unit may therefore advantageously issue multiple commands to the CPU interface regardless of the ready state of the devices involved in each command. When a peripheral or peripheral interface is receptive, a command may be issued to the peripheral or peripheral interface, and temporarily stored until the corresponding device is able to execute the command. Temporarily storing one or more commands in command buffers associated with a memory interface allows the memory interface to set up and execute multiple commands in a more expeditious manner. Additionally, temporarily storing data in buffers during data transfer operations allows the devices in the electronic system to transfer data in a continuous and uninterrupted flow, thereby allowing the electronic system to operate in a more efficient manner.


REFERENCES:
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patent: 5274795 (1993-12-01), Vachon
patent: 5530893 (1996-06-01), Sugi
patent: 5574944 (1996-11-01), Stager
patent: 6363439 (2002-03-01), Battles et al.
patent: 6442475 (2002-08-01), Utsui et al.

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