Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-09-21
2009-08-11
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07574566
ABSTRACT:
Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the memory request, a cache may provide both a trap signal and coherence information to the processor thread of the processing unit. After receiving the trap signal and the coherence information, the processor thread may perform a cache coherence operation for the memory request using at least the received coherence information. The processing unit may include a plurality of processor threads and a load balancer. The load balancer may receive coherence requests from one or more remote processing units and distribute the received coherence requests across the plurality of processor threads. The load balance may preferentially distribute the received coherence requests across the plurality of processor threads based on the operation state of the processor threads.
REFERENCES:
patent: 5893153 (1999-04-01), Tzeng
patent: 5893160 (1999-04-01), Loewenstein
patent: 6272602 (2001-08-01), Singhal
patent: 6711662 (2004-03-01), Peir
patent: 6751710 (2004-06-01), Gharachorloo
patent: 7017012 (2006-03-01), Clarke
patent: 7124253 (2006-10-01), Wright
patent: 2004/0025165 (2004-02-01), Desoli et al.
patent: 2005/0021914 (2005-01-01), Chung
patent: 2006/0101209 (2006-05-01), Lais
patent: 2007/0022253 (2007-01-01), Cypher
D. Chaiken, J. Kubiatowicz, and A. Agrawal, “Limitless Directories: A Scalable Cache Coherence Scheme”, In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV), pp. 224-234, IEEE Computer Society, Apr. 1991.
D. Chaiken and A. Agarwal, “Software-Extended Coherent Shared Memory: Performance and Cost”, In Proceedings of the 21st International Symposium on Computer Architecture (ISCA), pp. 314-324, IEEE Computer Society, Apr. 1994.
H. Grahn and P. Stenstrom, “Efficient Strategies for Software-Only Directory Protocols in Shared-Memory Multiprocessors”, In Proceedings of the 22nd International Symposium on Computer Architecture (ISCA), pp. 38-47, IEEE Computer Society, Jun. 1995.
M. Chaudhuri and M. Heinrich, “SMTp: An Architecture for Next-generation Scalable Multi-threading”, In Proceedings of the 31st International Symposium on Computer Architecture (ISCA), pp. 124-135, IEEE Computer Society, Jun. 2004.
Dudek Edward J
Kim Matt
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
LandOfFree
System and method for efficient software cache coherence does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for efficient software cache coherence, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for efficient software cache coherence will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4098218