System and method for efficient packing data into an output buff

Details System and method for efficient packing data into an output buff System and method for efficient packing data into an output buff

1996-11-18

1999-05-11

Lall, Parshotam S.

395561, 395564, 39580004, 39580006, 39580016, G06F9/00;13/00

Patent

active

059037792

ABSTRACT:
Vector data buffer apparatus for interfacing processor bus and register having different word sizes. The vector data buffer includes a word buffer for positioning data words into any desired position by rotation or reverse loading. Endian buffer further provides byte rotation and selectable endian word formation. Latches and selection multiplexers provided for shifting bytes into a wide register to effect register access with only a single processor I/O operation for improved performance of the processor.

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patent: 5560030 (1996-09-01), Guttag et al.
patent: 5594919 (1997-01-01), Turkowski
patent: 5819117 (1998-10-01), Hansen

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