Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-18
2002-10-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S116000, C716S030000, C716S030000, C716S030000, C716S030000, C370S474000, C714S045000, C714S724000, C326S041000, C703S014000
Reexamination Certificate
active
06470484
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and systems for locating circuitry cells on the die area of an integrated circuit and, more particularly, to methods and systems for efficiently locating circuitry cells not implementing a portion of the integrated circuit function.
BACKGROUND OF THE INVENTION
The design of an integrated circuit requires both a logical design and a physical layout. The logical design includes the determination of the interconnections between functional cells to implement the intended function of an integrated circuit. Functional cells are usually groups of transistors that implement a fundamental logical function such as an inverter or a logical OR function. The logical design of an integrated circuit determines the number of functional cells required for an integrated circuit. While the functional cells that implement the logic of an integrated circuit are the only cells required for an integrated circuit, other logical functions are usually included in an integrated circuit. One additional logical function is test circuitry. Test circuitry is usually provided for design debugging and troubleshooting. Typically, test circuitry includes a buffer for conditioning signals and electrically isolating the test circuitry from the functional logic of the integrated circuit when the test circuitry is not being used. When activated, test circuitry couples normally unavailable signals from the functional logic of the integrated circuit to the output pads for observation. In this document, cells used for other logical functions that do not directly implement the function of the integrated circuit are called functionally extraneous cells.
Once the logical design for the functional logic of an integrated circuit and any other logical functions is complete, the physical layout of the cells must be determined. Typically, layout tools implemented with computer programs are used to locate the cells required for the logical design of an integrated circuit. These layout tools may use certain constraints for placement of the functional cells. For example, input and output buffers are typically located in proximity to the input and output pads for the integrated circuit. Other functionally extraneous cells are distributed throughout the area of the die on which the cells are arranged for the integrated circuit. Once the cells are located on the die by a layout tool, the tool determines the interconnections between the cells that correspond to the logical design of the integrated circuit.
One problem that arises from the use of layout tools is a typical constraint of layout tools to balance the interconnections between cells to minimize problems caused by the capacitance and resistance of interconnections. That is, a layout tool attempts to locate cells so the interconnections between cells are approximately the same length. In this manner, the performance of one cell is not significantly impacted by signal transmission over interconnections having a length that is long relative to interconnections between other cells. While this constraint is generally useful when the cells being interconnected form a portion of the functional logic of the integrated circuit, it is not necessarily efficient when a cell being interconnected is a functionally extraneous cell. For example, a cell containing test circuitry, such as a signal multiplexer, may have a cell having signal buffers in it, interposed between the multiplexer and a state machine that comprises the functional logic of the integrated circuit. If the buffer cell, multiplexer cell, and a state machine cell are all located equally from one another, the length of the interconnection required between the state machine cell and the buffer may affect the state machine timing. That is, the shorter the interconnection between the buffer and state machine cells, the less adverse the impact of the capacitance and resistance of the interconnection between the buffer and state machine is on the state machine timing.
What is needed is a method for differentiating between functionally extraneous cells and logical functional cells for locating cells on an integrated circuit die.
What is needed is a method for interconnecting functionally extraneous cells with logically functional cells to minimize the impact of the functionally extraneous cells on the logically functional cells.
SUMMARY OF THE INVENTION
The above-noted limitations of previously known systems and methods for locating cells on a die of an integrated circuit have been overcome by a system and method operating in accordance with the principles of the present invention. The method of the present invention is comprised of defining the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool includes the first functionally extraneous cell without functionally coupling the first functionally extraneous cell to a second functionally extraneous cell; and altering the description of the first functionally extraneous cell so that the layout tool produces a second layout of the die that functionally couples said first functionally extraneous cell to said second functionally extraneous cell whereby the position of the second functionally extraneous cell with respect to a logically functional cell does not change between the first and second layouts. The description of the functionally extraneous cell complies with the description constraint for cells. However, by describing the functionally extraneous cell so that it is not functionally coupled to a logically functional cell, the layout tool locates the functionally extraneous cell closer to the logically functional cell than if the functionally extraneous cell is functionally coupled to both the logically functional cell and another functionally extraneous cell. In this manner, the advantages of the layout tool may be used to most efficiently locate the cells of the logically functional cells and then couple test circuitry or other functionally extraneous cells without adversely impacting the operation of the functional logic in a significant way.
These and other advantages and features of the present invention may be discerned from reviewing the accompanying drawings and the detailed description of the invention.
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Day Brian A.
Gauvin Coralyn S.
Barnes & Thornburg
Liu Andrea
LSI Logic Corporation
Smith Matthew
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