Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-12-04
2004-11-02
Robertson, David L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C714S006130
Reexamination Certificate
active
06813688
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer data storage systems, and more particularly to disk mirroring techniques in computer data storage systems.
2. Description of the Related Art
A typical computer system includes one or more hard disk drives (i.e., disk drives) for storing data. While the reliabilities of disk drives continue to improve, it is only a matter of time before a given disk drive fails. Data storage systems commonly implement one of several redundant array of inexpensive/independent disks (RAID) techniques in order to allow stored data to remain available despite a failure of one of the disk drives.
RAID level 1, or disk mirroring, stores identical copies of data on two different disk drives. Disk mirroring involves the exact replication of data. A mirrored disk array uses twice as many disks as a non-redundant disk array. Data written to one disk is also written to a redundant disk, such that there are always two physical copies of the same information. When data is read, it can be retrieved from the disk with the shorter queuing, seek, and rotational delays. If a disk drive of a RAID-1 system fails, the other copy is used to service requests and reconstruct a new mirrored disk. Disk mirroring is frequently used in database applications where availability and transaction rates are more important than storage efficiency. Since a block of data needs to be written to two different locations, a write performance penalty may be associated with mirroring.
Intelligent/Integrated drive electronics (IDE) is an interface technology for mass storage devices (e.g., disk drives) wherein the controller is integrated into the drive, and AT Attachment (ATA) is a disk drive interface standard. The two terms and their acronyms are often used interchangeably. Several versions of the ATA standard exist, including the basic ATA standard, Fast ATA, ATA-2, Fast ATA-2, ATA-3, and Ultra ATA. As used herein, the term “AT attachment” and the acronyms “ATA” and “IDE” refer to all variants of ATA-type or IDE-type interfaces. The basic ATA standard (ANSI X3.221-1994) supports a single 16-bit parallel data channel which may be shared by two separate devices configured as master and slave.
Today's disk drive market consists mainly of AT attachment (ATA), small computer systems interface (SCSI) and fibre channel drives. Fibre channel and SCSI drives are employed in enterprise class storage systems, while ATA drives are often limited to desktop applications. At the time of this disclosure, ATA drives are often a factor of between 2 to 3 times cheaper than SCSI drives. The ATA bus is a shared bus between a host and a maximum of 2 ATA drives.
When two ATA drives are connected to an ATA bus, they are popularly referred to as a master/slave pair. Both the master and slave drives include a set of interface registers that provide control and status information. Whenever the host writes to a register, the information is written into the corresponding registers of both the master drive and the slave drive. For example, during ATA operations, the host selects the desired drive by writing 0 (selects master drive) or 1 (selects slave drive) to a drive selection bit in an ATA device/head register. The host then writes a command to an ATA command register. Both the master drive and the slave drive check the device selection bit, and only the selected drive executes the command and responds to the host.
FIG. 1
is a diagram of one embodiment of a typical computer system
10
including a host
12
coupled to two devices
16
A-
16
B via an ATA controller
14
and an ATA bus
18
. Devices
16
A and
16
B include ATA interfaces, and may be ATA storage devices. Examples of ATA storage devices include hard disk drives, compact disk read only memory (CD-ROM) drives, and tape drives. Devices
16
A and
16
B in
FIG. 1
are configured to form a “master/slave” device pair according to the ATA standards. Either device
16
A or device
16
B is configured to be a “master” device, and the other device
16
is configured to be a “slave” device. Host
12
accesses devices
16
A and
16
B via ATA controller
14
and ATA bus
18
. The current ATA standards allow one or two devices to be coupled to host
12
via ATA controller
14
. It is noted that many computer systems include two ATA controllers, thus allowing up to four devices with ATA interfaces to be coupled to a host.
In the known embodiment of
FIG. 1
, ATA bus
18
is typically implemented as a flat ribbon cable having multiple conductors with three connectors attached thereto. A first of the three connectors is located at one end of the ribbon cable, and the other two connectors are positioned close together near the other end of the ribbon cable. ATA controller
14
is coupled to the first connector, and devices
16
A and
16
B are coupled to the other two connectors. ATA bus
18
acts as a “shared bus” coupling devices
16
A and
16
B to ATA controller
14
.
ATA bus
18
includes a data bus
20
, a control bus
22
, and a status bus
24
. Signal lines of data bus
20
are bidirectional signal lines which convey the ATA data signals between ATA controller
14
and devices
16
A and
16
B. The ATA data signals include data bus bit
0
(DD
0
) through DD
15
. Signal lines of control bus
22
convey the ATA control signals from ATA controller
14
to devices
16
A and
16
B. The ATA control signals include address signals and other control signals. The address signals include chip select 0 (CS
0
−), CS
1
−, device address bit
0
(DA
0
), DA
1
, and DA
2
. (The “−” symbol after a signal name indicates that the signal is active low; asserted when the signal is a logic low level and negated or deasserted when the signal is a logic high level.) The other control signals include input/output read (DIOR−), input/output write (DIOW−), direct memory access acknowledge (DMACK−), passed diagnostics (PDIAG−), and reset (RESET−).
Signal lines of status bus
24
convey the ATA status signals from device
16
A or device
16
B to ATA controller
14
. The ATA status signals include direct memory access request (DMARQ), interrupt request (INTRQ), and input/output ready (IORDY). As described above, the current ATA standards allow only one of the devices
16
A and
16
B to be selected at any given time. Only the selected device drives the signal lines of status bus
24
. Thus the current ATA standards rule out a situation where both devices
16
A and
16
B are driving one or more signal lines of status bus
24
at the same time.
In order to preclude a loss of critical data stored via disk drives, it is possible to implement a RAID 1 data storage system in the typical computer system
10
of FIG.
1
. In this situation, devices
16
A and
16
B may form a mirrored pair of disk drives. However, as only one of the mirrored pair of disk drives may be accessed at any given time, a significant amount of time is spent sequentially writing data to one disk drive of the mirrored pair, and then writing the same data to the other disk drive of the mirrored pair. First one ATA drive must be selected and written to, and then the other drive is selected and written to with the same data. It would thus be desirable to have a mechanism for more efficiently mirroring data in storage systems such as ATA systems in which conventionally only one drive on a port may be written to at a time.
SUMMARY OF THE INVENTION
A circuit comprising mirroring logic configured to couple to a controller, a first device, and a second device may be provided. Various methods for configuring first and second devices (e.g., data storage devices) to carry out a command from a controller simultaneously, which may be embodied within the mirroring logic, may be provided. A system including the mirroring logic, the controller, and the first and second devices may be provided. The first and second devices may include multiple registers. The mirroring logic may be configured to operate in a first connect mode wherein the mirroring log
Lee Whay S.
Talagala Nisha D.
Wu Chia Y.
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Robertson David L.
Sun Microsystems Inc.
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