Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-06-29
2002-06-04
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S190000, C365S205000
Reexamination Certificate
active
06400629
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit memories and more specifically to an integrated circuit memory, especially a dynamic random access memory (DRAM), in which stored contents are sensed from small voltage signals present on bitlines.
BACKGROUND
Existing DRAMs are generally slower to access than static random access memory (SRAM) or read only memory (ROM). Conventionally, DRAMs have been manufactured as standalone independent integrated circuit chips which store large quantities of data for faster access than magnetic or optical disk media, at relatively low prices and low power consumption. SRAMs and ROMs, by contrast, have usually provided faster access than DRAMs, but often at higher prices and power consumption because these memory types require a larger device count per stored data bit, which adds to cost and density.
Recently, interest has increased in using DRAMs as one of several elements of an integrated circuit, e.g. a “system on a chip”, which may also include logic or linear circuits or other circuit types. Such DRAM elements have been called embedded DRAM or “EDRAM”. The goals of using embedded DRAM include obtaining potentially large amounts of easily rewriteable storage with fast access times but at lower cost and power consumption than SRAMs. One problem facing existing DRAMs is that it takes longer to write a memory cell with a new datum than it takes to read or refresh the datum in that memory cell. This problem is understood with reference to
FIGS. 1 and 2
. Specifically,
FIG. 1
shows signals which are active when a prior art DRAM memory cell is being read. A read operation begins with the wordline voltage
10
rising from a quiescent value (in this case, about −0.4 volts) to an activated value which makes the access transistor of the memory cell conduct. Charge stored by a capacitor in the memory cell then begins to flow through the transistor on a bitline to a sense amplifier. At the sense amplifier a small voltage difference signal
11
develops between the voltage
12
on a bitline BT and the voltage
14
on a reference bitline BC which is not connected to the memory cell being read. The sense amplifier functions to convert a small swing, e.g. “analog” signal between the bitline BT and the reference bitline BC into a full swing logic level signal for storage to or transfer of the datum from the memory cell. After the small voltage signal
11
appears, the sense amplifier is set, i.e. triggered through a signal SETP
16
, to amplify the small voltage signal
11
to full swing logic levels. This results in the bitline voltage
12
and the reference bitline voltage
14
separating from their initial small voltage difference to respective predetermined high and predetermined low logic levels, in this case about 1.2 V, and 0.0 V, respectively. The voltage stored in the memory cell is shown in
FIG. 1
by curve
18
.
By contrast, some write operations in conventional DRAMs take longer to perform than a read operation. With reference to
FIG. 2
, an operation to write a high logic level, i.e. a “1” in a memory cell that currently stores a low logic level, i.e. a “0” is known as “Read
—
0_Modify_Write
—
1.” This write operation starts by reading the memory cell which contains a “0” and then forcing the memory cell to store the opposite value “1.” The initial reading step is necessary to prevent the stored contents of memory cells on adjacent bitlines from becoming corrupted. While the one memory cell is being rewritten with a “1” from a “
0
” state, memory cells on other bitlines accessed by the same wordline are read and “written back” with the same data that they already store.
As shown in
FIG. 2
, the read_modify_write operation begins the same way as the read operation with the wordline voltage
10
rising from the quiescent value to an activated value. Charge stored by a capacitor in the memory cell then begins to flow through the transistor on a bitline to a sense amplifier, where a small voltage difference signal
21
develops between the voltage
22
on a bitline BT and the voltage
20
on a reference bitline BC which is not connected to the memory cell being written. After the small voltage signal
21
appears, the signal SETP
16
sets the sense amplifier, which results in the small voltage signal
21
being amplified into predetermined high and predetermined low logic levels on the reference bitline BC and the bitline BT, respectively, which reflect the original “0” value datum stored in the memory cell.
In the prior art DRAM operation shown in
FIG. 2
, the voltages
22
,
20
on the bitline BT and reference bitline BC are forced to new levels only after the sense amplifier is set. After the sense amplifier is set, the voltages
20
,
22
advance almost fully towards the high and low logic levels, respectively. Then, the bitline and reference bitline voltages reverse course to reach the opposite levels as required by the write operation.
The time required to perform the initial read before writing makes the voltage
24
in the memory cell take longer to rise than in the read operation. In comparison to the read operation shown in
FIG. 1
, in the read_modify_write operation, the memory cell voltage takes about 30% longer to rise to 90% of final value than it does in the read operation, as evident from comparing the intervals t
0
-t
1
of
FIG. 1
with t
0
′-t
1
′ of FIG.
2
.
Heretofore, the longer time to perform the read_modify_write operation has been considered acceptable. This is because forcing bitline signal levels to new values too soon could potentially corrupt data in other memory cells due to line to line noise coupling between the bitline being written and an adjacent bitline. Heretofore, there has not been a way to quickly write a memory cell with a new value without risking corruption of data in memory cells which are accessed by adjacent bitlines.
SUMMARY
Accordingly, among objects of the invention, each of which may operate in the alternative to, or in conjunction with other objects, are the following:
An object of the invention is to perform a write operation to a memory cell in about as little time as a read operation.
Another object of the invention is to quickly perform a write operation to a memory cell without risking corruption of data in memory cells accessed by adjacent bitlines.
Another object of the invention to provide a system in which precharging is performed in a conduction path through bitswitches coupled to the primary sense amplifiers.
Still another object of the invention is to perform a write operation by holding only one of a true bitline and a reference bitline at a fixed potential and setting a sense amplifier to amplify a small voltage difference between the true and reference bitlines into predetermined high and low logic levels for storing a datum into a memory cell.
Accordingly, in an aspect of the present invention, an integrated circuit including a memory is provided which is adapted to write a datum to a memory cell by bitswitches which hold only one of a true bitline and a reference bitline at a fixed potential when a sense amplifier is set, the sense amplifier being adapted to amplify a small voltage difference between the true and reference bitlines to a predetermined high voltage and a predetermined low voltage. The true bitline is then at one of the predetermined high voltage and the predetermined low voltage, and that voltage is transferred to the memory cell to write the datum.
In a more preferred aspect of the invention, the memory cell being written and other memory cells are accessed by a wordline. Bitswitches on such other memory cells not currently being written are adapted to isolate true and reference bitlines coupled to those memory cells when sense amplifiers coupled to those bitlines are set, such that the stored contents of such memory cells not being written are refreshed at the time that the selected memory cell is written.
REFERENCES:
patent: 4677592 (1987-06-01), Sakurai et al.
patent: 5007022 (1991-04-01), Leigh
patent: 5339274
Barth, Jr. John E.
Pilo Harold
Mai Son
Neff Daryl K.
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