Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-05-03
2001-05-08
Auve, Glenn A. (Department: 2781)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S322000
Reexamination Certificate
active
06230279
ABSTRACT:
BACKGROUND OF THE INVENTION
This application is based on Japanese Patent Application No. 9-145253, filed Jun. 3, 1997, the content of which is incorporated herein by reference.
The present invention relates to a computer system and a processing speed control method therefor and, more particularly, to a computer system that can variably control the Central Processing Unit processing speed so as to realize a power management function and a CPU processing speed control method used in the system.
Recently, various types of notebook personal computers which can be easily carried and operate on batteries have been developed. Various types of power saving functions are provided for such personal computers. The principal object of these power saving functions is to reduce the consumption of battery power so as to prolong the operating time. To save power consumption, the CPU processing speed is decreased.
With the recent improvement in the performance of microprocessors, the power consumption continues to increase. In portable computers, therefore, serious problems are posed in terms of heat dissipation measures for the microprocessors. For this reason, to reduce the power consumption by decreasing the CPU processing speed is important as a measure to prevent an excessive rise in the temperature of a microprocessor or the like.
In conventional CPU processing speed control techniques, when a CPU or a peripheral unit stops significant processing and waits for an event to take place, the clock rate is decreased or the supply of power is stopped to reduce the power consumption. Many such techniques have been known as described below.
(1) U.S. Pat. No. 4,137,563: Heat dissipation is suppressed by intermittently outputting minimum clock pulses necessary to operate a unit standing by.
(2) U.S. Pat. No. 4,381,552: The supply of clocks to the CPU and memory of the portable electronic device is stopped in an inoperative state.
(3) U.S. Pat. No. 4,851,897: The CPU clock is stopped while waiting for a key input or interruption. The supply of clocks to the I/O is not stopped. In general the processor waits for a long period of time in an idle loop. With this operation, therefore, the power consumption decreases, and the battery life can be greatly extended.
(4) U.S. Pat. No. 5,142,684: The low-speed second CPU with low power consumption is used to monitor the state of the system during an idle time. In this period, the power supply for the high-speed CPU is turned off. This high-speed CPU selects the clock rate in accordance with the task to be executed.
(5) U.S. Pat. No. 5,222,239: The clock frequency of the CPU is decreased when high system performance is not required.
(6) U.S. Pat. No. 5,452,401: The clocks to a plurality of units on one chip are turned on/off very quickly in accordance with the operation states of the units, thereby saving power and suppressing generation of heat.
(7) U.S. Pat. No. 5,560,017: The frequency of the system clock is decreased by the BIOS software while an event is waited for.
Various techniques have also been known for monitoring the temperature of a CPU and reducing the power consumption when the temperature is at a predetermined value or more. Furthermore, techniques, in combination with the above techniques, have been known for uniformly setting a CPU's processing speed as a user's choice without taking account of the details of the contents of the process performed by the CPU, such as the one which permits a user to alternately set a high performance mode and a power saving mode.
All these techniques only decrease the processing speed irrespective of the type of the software in execution, but have no mechanism for reflecting user's expectations and intentions with regard to the respective processing speeds of the individual software.
More specifically, the CPU processing speed cannot be dynamically changed at a user's wish while the user is working with the computer. These techniques cannot therefore meet user's requirements, e.g., giving higher priority to the processing speed than power saving in accordance with the contents of the currently executed task or decreasing the CPU processing speed in tasks other than specific tasks to prolong the life of the battery.
The conventional technique of decreasing the operating speed of the CPU by decreasing the clock rate is effective in extending the battery life. It should be noted, however, that this technique does not decrease the energy required for the execution of a given task.
Even if the clock rate of the CPU is decreased, there is no trade-off between the time required for the execution of a given task and the energy required therefor. In consideration of the power consumed by a CMOS logic circuit, the energy consumed by the CMOS logic circuit is proportional to the number of execution clocks/cycles in terms of linear approximation, but is not proportional to the execution time. Even if, therefore, the clock rate is changed, the amount of energy required to complete a given task remains the same as long as the number of clocks required to complete the task remains the same.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a computer system which can realize CPU processing speed control reflecting user's intentions, and harmonize the need to reduce the power consumption with the user's wish to obtain a comfortable execution speed, and a processing speed control method therefor.
It is another object of the present invention to provide a computer system which can trade off the time required to execute a given task against the energy required for the task, and a processing speed control method therefor.
According to the present invention, there is provided a computer system capable of variably controlling a processing speed of a CPU, comprising means for receiving an acceleration or deceleration instruction from a user by using a user interface which allows the user to instruct acceleration and deceleration of the processing speed of the CPU, means for changing the current processing speed of the CPU in accordance with the acceleration or deceleration instruction, and means for defining speed management data indicating a CPU processing speed for execution of each piece of software by recording a result obtained by changing the processing speed of the CPU in correspondence with software currently executed in the computer system, wherein the CPU processing speed can be controlled for each piece of software in accordance with the speed management data.
In this computer system, when acceleration or deceleration of the CPU processing speed is instructed by the user through an interface such as a hot key or a button on the display screen, the CPU processing speed is dynamically changed accordingly. The user can therefore dynamically change the current CPU processing speed by manipulating a hot key or button, and can freely change the processing speed in accordance with the contents of a task. This change is recorded as speed management data in correspondence with the name of software such as an application program which has been executed when the processing speed was changed. Every time the user instructs acceleration or deceleration of the CPU processing speed, speed management data is formed. By using the speed management data, the CPU processing speed can be controlled for each piece of software when it is executed. CPU processing speed control can therefore be performed in accordance with a user's intentions such that the CPU processing speed is increased when several specific pieces of software are executed, but decreased for other pieces of software to realize power saving and the like, thus harmonizing the need to reduce the power consumption with the user's wish to obtain a comfortable execution speed.
As a user interface for receiving CPU processing speed acceleration/deceleration instructions from the user, a key or button for instructing acceleration and a key or button for instructing deceleration are preferred. With these keys
Dewa Koichi
Sato Fumitaka
Yamaki Masayo
Auve Glenn A.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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