Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-12-02
2003-07-08
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S112000, C710S041000
Reexamination Certificate
active
06591350
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to controlling memory access prioritization, and particularly to a system and method for dynamically varying memory access prioritization in a controller for a disk drive device.
2. Background of the Invention
Existing hard disk drive systems typically include a hard disk controller for, among other things, receiving and storing data retrieved from the storage disk prior to the retrieved data being transported to a host external to the disk drive system. Hard disk drive controllers conventionally include a read channel interface block for receiving data retrieved from the storage disk and placed on a read channel, and a buffer for temporarily storing the retrieved data and including a memory controller for controlling a separate memory device, such as a random access memory (RAM). The hard disk controller further includes a host interface for sending the retrieved data to the external host. A processing element in the hard disk controller performs functions that are not handled in hardware, such as processing servo information regarding the location of the head relative to the tracks on the storage disk, recovering from error conditions and configuring the disk drive system after power up.
The processing element typically utilizes off-chip memory, such as flash memory, that is dedicated to storing instructions and data for execution by the processing element. Because a dedicated flash memory is substantially slower than the RAM device associated with the buffer, existing or planned hard disk controllers have utilized the memory device associated with the buffer for storing some instructions and related data for execution by the processing element.
The RAM device associated with the buffer may store information corresponding to a number of different sources and/or function blocks within the conventional hard disk controller. Due to the fact that different sources/function blocks have different timing and bandwidth requirements in performing their intended functions, the buffer typically includes an arbitration block to prioritize memory access requests depending in part upon the particular sources/function blocks submitting the memory access requests. In this way, sources/function blocks within the hard disk controller access the RAM device based upon the individual timing and bandwidth requirements thereof.
In conventional hard disk controllers, the processing element is provided a relatively low priority to access the RAM device associated with the buffer. In most instances the processing element is capable of performing as planned while having assigned a lower priority relative to the other function blocks in the hard disk controller. The performance of the processing element and the hard disk controller in general is adversely affected, however, when the processing element processes certain interrupts. In particular, the processing element occasionally needs to relatively quickly handle certain interrupts, such as interrupts which indicate that the disk drive device has moved or that there is a problem with the spin speed of the disk drive device. If the processing element is waiting to complete a fetch from the RAM device when such an interrupt arrives, the processing element must wait until the fetch operation is complete before handling the interrupt. Because the processing element may oftentimes have to wait for an extended period of time before being granted access to the RAM device, the time delay before the processing element handles the interrupt may substantially hinder the performance of the disk drive system. Based upon the foregoing, there is a need for the processing element to effectively handle certain events without adversely effecting the performance of the other function and/or functional blocks in the hard disk controller.
SUMMARY OF THE INVENTION
The present invention overcomes the shortcomings in prior systems and thereby satisfies a significant need for a hard disk controller in which the processing element thereof relatively quickly performs certain operations, such as handling certain interrupts, without noticeably impacting the performance of other portions of the hard disk controller. In a preferred embodiment of the present invention, the hard disk controller dynamically modifies the priorities assigned to memory requests submitted by various function blocks in the hard disk controller in response to a particular function block, having submitted a memory request that was assigned a lower priority, requiring the memory request be completed sooner than the request would otherwise be completed.
Specifically, the hard disk controller includes a priority modification block which asserts a control signal upon the occurrence of an event. The event may be the reception, at the processing element, of one or more particular interrupts. The asserted control signal causes an arbitration block within the buffer to change the priorities of pending memory requests so that a memory request previously submitted by the processing element is assigned a higher priority relative to a priority level initially assigned to the memory request submitted by the processing element. The priority modification block de-asserts the control signal upon the memory request of the processing element being completed. Thereafter, memory requests subsequently submitted by the processing element are assigned the lower priority as before.
REFERENCES:
patent: 4819203 (1989-04-01), Shiroyanagi et al.
patent: 5524235 (1996-06-01), Larson et al.
patent: 6092158 (2000-07-01), Harriman et al.
patent: 6145052 (2000-11-01), Howe et al.
Bragdon Reginald G.
Jorgenson Lisa K.
STMicroelectronics Inc.
Szuwalski Andre
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