System and method for dynamic power management using data...

Details System and method for dynamic power management using data... System and method for dynamic power management using data...

2005-03-08

2005-03-08

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S156000, C713S300000, C713S322000, C713S340000, C710S056000, C710S057000, C365S226000

Reexamination Certificate

active

06865653

ABSTRACT:
A power management system for digital circuitry uses data buffer monitoring to determine appropriate processor clock speed or voltage. This allows a processor to be switched from a low power state to a high power state when a monitored data buffer level feeding data to a power intensive application is greater than a second memory buffer level. The processor is switched from a high power state to a low power state when the monitored data buffer level is less than a first memory buffer level.

REFERENCES:
patent: 6205078 (2001-03-01), Merritt
patent: 6510099 (2003-01-01), Wilcox et al.
patent: 20010043353 (2001-11-01), Iizuka et al.
patent: 20020169990 (2002-11-01), Sherburne

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