Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2008-01-08
2008-01-08
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S005000, C711S127000, C711S157000, C711S165000, C711S202000
Reexamination Certificate
active
07318114
ABSTRACT:
In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each decoder of a given memory controller may be independently configurable to match on a respective value of a subset of address bits such as the low-order cache line address bits, for example, received in a memory request. In one specific implementation, the number of decoders included on a given memory controller may correspond to the number of ways in which the memory is interleaved.
REFERENCES:
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patent: 4853846 (1989-08-01), Johnson et al.
patent: 5530837 (1996-06-01), Williams et al.
patent: 6381668 (2002-04-01), Lunteren
patent: 6473845 (2002-10-01), Hornung et al.
Office Action from European Patent Application No. 05256336.8, filed Oct. 12, 2005, whose inventor is Robert Cypher.
“Using Hardware Counters to Automatically Improve Memory Performance”; Mustafa M. Tikir & Jeffrey K. Hollingsworth; Computer Sciences Department, University of Maryland, College Park, MD; pp. 1-12.
Curran Stephen J.
Lane Jack A.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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