System and method for diallocating stream from a stream buffer

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395460, G06F 1202

Patent

active

057375658

ABSTRACT:
A system and method to use stream filters to defer deallocation of a stream based on the activity level of the stream, thereby preventing a stream thrashing situation from occurring. The least recently used ("LRU") stream is deallocated only after a number of potential new streams are detected. In a data processing system, a method for prefetching cache lines from a main memory to an L1 cache coupled to a processor coupled by a bus to the main memory, wherein the prefetching is augmented with the utilization of a stream buffer and a stream filter, wherein the stream buffer includes an address buffer and a data buffer, wherein the stream buffer hold one or more active streams, and wherein the stream filter contains one or more entries corresponding to one or more active streams, the method comprising the steps of monitoring a sequence of L1 cache misses; replacing entries in the stream filter in response to the L1 cache misses on an LRU basis; and maintaining one of the one or more active streams in the stream buffer until all of the one or more entries corresponding to the one of the one or more active streams have been replaced by the replacing step.

REFERENCES:
patent: 4442488 (1984-04-01), Hall
patent: 4980823 (1990-12-01), Liu
patent: 5146578 (1992-09-01), Zangenehpour
patent: 5317718 (1994-05-01), Jouppi
patent: 5345560 (1994-09-01), Miura et al.
patent: 5353419 (1994-10-01), Touch et al.
patent: 5361391 (1994-11-01), Westberg
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5388247 (1995-02-01), Goodwin et al.
patent: 5473764 (1995-12-01), Chi
patent: 5490113 (1996-02-01), Tatosian et al.
patent: 5566324 (1996-10-01), Kass
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5586295 (1996-12-01), Tran
MC88110 Second Generation RISC Microprocesser User+s Manual, 1991.
Dahlgren and Stenstrom, "Effectiveness of Hardware-Based Stride and Sequential Prefetcthing in Shared-Memory Multiprocessors", High Performance Computer Architecture, 1995 Symposium, pp. 68-77, Feb. 1995.
Chen and Baer, "Effective Hardware-Based Data Prefetching for High-Performance Processors", IEEE Transactions on Computers, V.44, No. 5, pp. 609-623, May 1995.
Chiueh, Tzi-cker, "Sunder: A Programmable Hardware Prefetch Architecture for Numerical Loops", Supercomputing '94, pp. 488-497.
Farkas, Jouppi, and Chow, "How Useful Are Non-blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors", High Performance Computer Architecture, 1995 Symposium, pp. 78-89, Feb. 1995.
Palacharla and Kessler, "Evaluating Stream Buffers as a Secondary Cache Replacement", Computer Architecture, 1994 International Symposium, pp. 24-33.
Evaluating Stream Buffers as a Secondary Cache Replacement, S.Palacharla and R. Kessler, 1994 IEEE 1063-6879/94.
U.S. application No. 08/442,740.

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