Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-03-28
1998-09-15
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711133, 711138, 711167, G06F 1208
Patent
active
058095233
ABSTRACT:
A system, method and computer program product which determines the relative performance of a local cache and renders the resultant performance increase (or in certain circumstances, the decrease) in cache performance of a stand-alone computer or networked "client" perceptible to the user in an especially intuitive manner. By accurately tracking and factoring in the times and amounts of data read from one or more source locations and the cache, the amount of time required to execute "read" operations without the cache can be determined. By dividing this time period by the actual time to execute the "read", the true relative performance of the cache may be determined.
REFERENCES:
patent: 4833642 (1989-05-01), Ooi
Berliner Brian
Kayes Kevin W.
Schaffer Daniel H.
Bragdon Reginald G.
Chan Eddie P.
Kelly Robert H.
Kubida William J.
Sun Microsystems Inc.
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