System and method for determining probing locations on IC

Details System and method for determining probing locations on IC System and method for determining probing locations on IC

2007-08-14

2007-08-14

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C714S025000, C438S016000

Reexamination Certificate

active

11471068

ABSTRACT:
An apparatus and method for tracing back a probing location to identify the circuit element being probed on a device under test (DUT). The coordinates of the irregularity on the DUT are used to trace back to the logic cone to decipher the root-cause of the irregularity. The Def and Lef files are interrogated using the coordinates to obtain the cell and net data to enable the investigation. Additionally, a schematic viewer is used to investigate the logic cone to potential root-causes for the irregularities.

REFERENCES:
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6608494 (2003-08-01), Bruce et al.
patent: 6788093 (2004-09-01), Aitren et al.
Desplats, Romain, et. al., “IC Diagnostic with Time Resolved Photon Emission and CAD Auto-channeling,”Proceedings from the 29thInternational Symposium for Testing and Failure Analysis, Nov. 2-6, 2003, Santa Clara, California.
“LAVIS: The Future of Layout Viewer,” Mar. 2005, Tool Corporation.

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