System and method for determining probing locations on IC

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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C700S096000

Reexamination Certificate

active

11345004

ABSTRACT:
A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. A driving signal is applied to a stage to align a prober with the location to be probed.

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Desplats, Romain, et. al., “IC Diagnostic with Time Resolved Photon Emission and CAD Auto-channeling,”Proceedings from the 29thInternational Symposium for Testing and Failure Analysis, Nov. 2-6, 2003, Santa Clara, California.
“LAVIS: The Future of Layout Viewer,” Mar. 2005, Tool Corporation.

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