System and method for determining on-chip bit error rate...

Details System and method for determining on-chip bit error rate... System and method for determining on-chip bit error rate...

2006-06-28

2008-12-30

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S738000, C714S025000, C714S735000, C375S221000, C370S236100

Reexamination Certificate

active

07472318

ABSTRACT:
A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD may be determined from within the PLD based on a comparison of at least a portion of the generated test packets with at least a portion of the generated test packets transmitted over the closed communication path received by the PLD via the closed communication path from the remote PLD. A transmit path of the PLD may be internally coupled to a receive path of the PLD, and a receive path of the PLD may be internally coupled to a transmit path of the PLD. The PLD may be internally configured to operate in an internal optical loopback mode or an internal electrical loopback mode.

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