Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-04
2006-07-04
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07073152
ABSTRACT:
Systems, methods, and software products determine a highest level signal name in a hierarchical circuit design. A signal path is traced into a hierarchically lower level of the circuit design from a predetermined net in the circuit design to a predetermined terminal instance, while adding indicia, to an instance history list, of each subsequent instance encountered. A port instance is determined on the terminal instance associated with a selected net for which the highest level signal name is to be determined. The selected net is designated as the current net. For each stored indicia in the instance history list, the net connected to the current net in a hierarchical parent of the instance identified by the indicia is determined, to establish a next current net. If a condition exists wherein there is no connection from the current net to a hierarchically higher level instance, then the current net is established as the highest level signal name for the selected net.
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Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,682, Entitled: Method And Program Product For Determining Nets Requiring Detailed Electromigration And Self Heating Analysis In A Digital Integrated Circuit; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,698, Entitled: Method And Program Product For Performing Self-Heating Analysis In A Digital Integrated Circuit Through A Single Cycle Transient Simulation; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,376, Entitled: Method And Program For Visual Display and One-Click Repair Of Electromigration And Self Heating Design-Rule Violations In A Digital Integrated Circuit Layout Database; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,501, Entitled: Method And Program Product For Performing Electromigration Analysis In A Digital Integrated Circuit By Converting A Netlist To A DC Model And Performing DC Analysis Of The DC Model; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,528, Entitled: Method And Program Product For Performing A Worst Case Electromigration And Self-Heating Analysis In A Digital Integrated Circuit With Worst-Case Superposition Of Partial Currents; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,692, Entitled: Method And Program Product For Performing Electromigration Analysis In A Digital Integrated Circuit Through A Single Cycle Transient Simulation; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Lelm, Charles A.; U.S. Appl. No. 10/706,508, Entitled: Method And Program Product For Performing Self-Heating Analysis In A Digital Integrated Circuit Layout Database by Substituting Resistive Models For Active Devices; Filed Nov. 12, 2003.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655516US; Entitled: Method And Program Product For Determining Worst Case Currents In A Digital Integrated Circuit Through Worst-Case Superposition Of Partial Currents; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655564US; Entitled: Systems And Methods For Re-Using Circuit Design Analysis Results; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655581US; Entitled: System And Method For Determining Detail Of Analysis In A Circuit Design; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655595US; Entitled: Systems And Methods That Identify Equivalent Instantiation-Specific Configuration Information For Analysis Tools; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H. & Stevens, Scott Alan; U.S. Patent Application filed under EV210655520US; Entitled: System And Method To Limit Analyzed Current Flow In A Circuit Design; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655533US; Entitled: System And Method For Processing Configuration Information; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655555US; Entitled: System And Method For Balancing Run-Time And Result Accuracy In A Circuit Design Analysis Tool; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655578US; Entitled: System And Method For Indicating Logic State Combinations Used During Circuit Design Analysis; Filed Jan. 30, 2004.
Keller, S. Brandon; Rogers, Dennis R.; Robberts, George H.; U.S. Patent Application filed under EV210655547US; Entitled: System And Method For Determining Control Signal Combinations For Use During Simulation Of A Stage Of A Circuit Design; Filed Jan. 30, 2004.
Keller S. Brandon
Robbert George Harold
Rogers Gregory Dennis
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