System and method for determining a bus address on an add-in...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring

Reexamination Certificate

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Details

C710S009000, C710S301000, C710S302000

Reexamination Certificate

active

07827333

ABSTRACT:
One embodiment of the present invention sets forth a technique to determine a bus address for an add-in card on a System Management bus (SMbus) that includes a hybrid microcontroller (hEC) and discrete graphics processing unit (dGPU). A graphics driver requests the System Basic Input/Output System (SBIOS) for a list of available slave addresses. The graphics driver receives the list and selects an available slave address to be assigned to the hEC. The graphics driver assigns the selected address to the hEC through an Inter-Integrated Circuit bus backdoor. The graphics driver then passes the selected address back to the SBIOS and the selected address is removed from the list of available addresses. Advantageously, this approach to dynamically assigning bus addresses provides compatibility with different types of hECs as well as with different motherboard configurations and other SMbus devices.

REFERENCES:
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5276813 (1994-01-01), Elliott et al.
patent: 5600354 (1997-02-01), Hackleman et al.
patent: 6070207 (2000-05-01), Bell
patent: 6363423 (2002-03-01), Chiles et al.
patent: 6546425 (2003-04-01), Hanson et al.
patent: 6546435 (2003-04-01), Yoshimura et al.
patent: 6708230 (2004-03-01), Shin
patent: 6832270 (2004-12-01), Das Sharma et al.
patent: 6928503 (2005-08-01), Mosgrove
patent: 6956579 (2005-10-01), Diard et al.
patent: 7007080 (2006-02-01), Wilson
patent: 7065630 (2006-06-01), Ledebohm et al.
patent: 7269832 (2007-09-01), Bodin et al.
patent: 7337036 (2008-02-01), Pedrini et al.
patent: 7437494 (2008-10-01), Ellerbrock
patent: 7707437 (2010-04-01), Berenbaum et al.
patent: 2001/0044860 (2001-11-01), Hinrichs et al.
patent: 2003/0149821 (2003-08-01), Matsui et al.
patent: 2003/0188062 (2003-10-01), Luse et al.
patent: 2006/0282604 (2006-12-01), Temkine et al.
patent: 2007/0245046 (2007-10-01), Asaro et al.
patent: 2008/0028181 (2008-01-01), Tong et al.
patent: 1631042 (2006-03-01), None
patent: 2000209209 (2000-07-01), None
patent: 2001136171 (2001-05-01), None
patent: 200337788 (2003-11-01), None
patent: WO 2007074283 (2007-07-01), None
Maamoun et al., “Interfacing in Microprocessor-based Systems with a Fast Physical Addressing”, 2003, IEEE, Proceedings of the 3rd IEEE International Workshop on system-on-Chip for Real-Time Applications, pp. 1-6.
Johansson, Peter, “Virtual Node IDs”, Oct. 15, 1998, Congruent Software, Inc., pp. 1-6.
James, David V., “Scalable I/O Architecture for Buses”, 1989, IEEE, COMPCON Spring '89, pp. 539-544.

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