Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-10-13
2001-11-13
Auve, Glenn A. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S042000, C714S711000, C714S718000, C714S733000
Reexamination Certificate
active
06317846
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer memories, and in particular to built-in self-test techniques for embedded memories.
BACKGROUND OF THE INVENTION
Computer memory arrays on chips involve a very large number of individual cells. For dynamic random access memories, the number of cells is very large. As a result, even small defect rates arising out of the manufacturing process result in an unacceptably low yield. Test procedures are applied to DRAM chips, usually on wafer-by-wafer basis. Every chip on each wafer is tested on specialized equipment, which identifies the locations of defective cells. Location information is then supplied to a controller for a laser repair device, which achieves a hardware fix. The repaired wafer is then tested again.
Such test and repair procedures are expensive because of the need to employ specialized test and repair equipment.
In SRAM chips, and other chips with embedded logic, repairs are not ordinarily carried out. The size of arrays in SRAM chips and other such chips has been small enough that, even without repairs, acceptable yield is obtained. Also, because SRAM chips are generally more specialized and manufactured in smaller quantities, the cost of configuring laser repair machines must be averaged over a relatively small number of wafers, when compared to DRAM chips.
In chips with embedded memories, it has become possible to have test procedures carried out by logic on the chip, known as built-in self-test units. The built-in self-test units for SRAM chips carry out a verification process resulting in a simple indication of whether there is a defect in the memory array. As defective chips are simply discarded, no additional information is required.
However, array size in SRAM chips is steadily increasing. Accuracy in manufacturing techniques is not increasing sufficiently rapidly to maintain yields. Furthermore, additional components, which were formerly in separate devices, are also being added to SRAM chips. The added components increase functionality of the chips, and are sometimes referred to as a system on a chip. These devices mean that individual chips are much more expensive, making discarding faulty chips undesirable.
SUMMARY OF THE INVENTION
According to an aspect of the invention, a method is provided for determining the location of faulty components in a computer memory array on a chip and for providing a software repair procedure. According to the method, the location of faulty components in a computer memory array is determined by successively reading and writing to locations in the array according to an algorithm. If a faulty component is detected, it is determined whether a spare component in a spare memory array on the chip is available. If a spare component is available, a spare component is designated to correspond to the faulty component. A look up table on the same chip stores information representing the location of the faulty component associated with information representing the location of the corresponding spare component. The method may also include, testing the memory array by successively reading and writing to locations on the memory array according to an algorithm, during which step, when a faulty component with which a spare component is associated is addressed, the look up table is used to identify the spare component corresponding to the faulty component, and the spare component is addressed.
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Higgins Frank P.
Kim Ilyoung
Zorian Yervant
Agere Systems Guardian Corp.
Auve Glenn A.
Duane Morris & Heckscher LLP
Phan Raymond N
Rosenthal Robert E.
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