System and method for detecting and preventing race...

Details System and method for detecting and preventing race... System and method for detecting and preventing race...

2005-04-26

2008-12-02

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

Reexamination Certificate

active

07461305

ABSTRACT:
A system and method for detecting and preventing race conditions in a circuit is provided. The system includes a first memory element for receiving a data stream. The system further includes a plurality of additional memory elements for directly receiving an output of the data stream from the first memory element. Delay elements are defined between the first memory element and the plurality of additional memory elements other than a second memory element, so that each delay element between the first memory element and the plurality of additional memory elements other than the second memory element are combined to define a sum delay. A plurality of comparators are connected to the plurality of memory elements such that each comparator being configured to compare an input to the first memory element and an output of each of the plurality of additional memory elements. The output from the comparator helps to identify whether a race condition is present between the first memory element and any one of the plurality of additional memory elements.

REFERENCES:
patent: 5608645 (1997-03-01), Spyrou
patent: 6915462 (2005-07-01), Davis et al.
patent: 7236555 (2007-06-01), Brewer
patent: 2002/0009169 (2002-01-01), Watanabe

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