Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Virtual machine memory addressing
Reexamination Certificate
2005-11-01
2005-11-01
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Virtual machine memory addressing
C711S148000, C711S203000
Reexamination Certificate
active
06961806
ABSTRACT:
A computer system includes at least one virtual machine that has a plurality of virtual processors all running on an underlying hardware platform. A software interface layer such as a virtual machine monitor establishes traces on primary structures located in a common memory space as needed for the different virtual processors. Whenever any one of the virtual processors generates a trace event, such as accessing a traced structure, then a notification is sent to at least the other virtual processors that have a trace on the accessed primary structure. In some applications, the VMM derives and maintains secondary structures corresponding to the primary structures, such as where the VMM converts, through binary translation, original code intended to run on a virtual processor into code that can be run on an underlying physical processor of the hardware platform. In these applications, the VMM may rederive or invalidate the secondary structures as needed upon receipt of the notification of the trace event. Different semantics are provided for the notification, providing different choices of performance versus guaranteed consistency between primary and secondary structures. In the preferred embodiment of the invention, a dedicated sub-system is included within the VMM for each virtual processor; each sub-system establishes traces, senses trace events, issues the notification, and performs other operations relating specifically to its respective virtual processor.
REFERENCES:
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5319760 (1994-06-01), Mason et al.
patent: 5511217 (1996-04-01), Nakajima et al.
patent: 5553291 (1996-09-01), Tanaka et al.
patent: 5893144 (1999-04-01), Wood et al.
patent: 6075938 (2000-06-01), Bugnion
patent: 6173395 (2001-01-01), Wisor et al.
patent: 6397242 (2002-05-01), Devine et al.
patent: 6785886 (2004-08-01), Lim et al.
“Implementing Efficient Fault Containment for Multiprocessors,” Mendel Rosenblum; et al., Communications of the ACM, vol. 39, No. 9, pp. 52-61, Sep. 1996.
“Hive: Fault Containment for Shared-Memory Multiprocessors,” John Chapin, et al., Computer Systems Laboratory, Stanford University, also appearing in 15th ACM Symposium on Operating Systems Principles, Dec. 1995.
Agesen Ole
Bugnlon Edouard
Devine Scott W.
Rosenblum Mendel
Subrahmanyam Pratap
Elmore Reba I.
Pearce Jeffrey
VMware, Inc.
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