System and method for designing a low leakage monotonic CMOS...

Details System and method for designing a low leakage monotonic CMOS... System and method for designing a low leakage monotonic CMOS...

2011-08-09

2011-08-09

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S106000, C716S132000

Reexamination Certificate

active

07996810

ABSTRACT:
A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.

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