Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-03
2006-10-03
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S002000
Reexamination Certificate
active
07117455
ABSTRACT:
The present invention is a system and method for optimizing electrical circuits by means of derivative-free optimization. Tunable parameters such as component values, transistor sizes or model parameters are automatically adjusted to obtain an optimal circuit. Any method of measuring the performance of the circuit, including computer simulation, can be incorporated into the optimization technique, with no derivative requirements. An arbitrary continuous optimization problem can be posed, including an objective function, equality and inequality constraints, and simple bounds on the tunable parameters. The optimization technique is efficient and guarantees that it will find a locally optimal solution from any starting point. Further, the procedure includes a method of automatically recovering from electrical failure to enable automatic and productive circuit optimization. A set of measurement widgets is provided to automatically introduce the checking required to recover from electrical failure. The automated circuit optimization leads to higher quality circuits, increases designer productivity, results in a better understanding of the tradeoffs inherent in the circuit and lifts the thinking of the circuit designer to a higher level.
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Restle Phillip
Scheinberg Katya
Visweswariah Chandramouli
Walker Steven G.
Garbowski Leigh M.
International Business Machines - Corporation
Keusey, Tutunjian & & Bitetto, P.C.
Perez-Pineiro, Esq. Rafael
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