System and method for defining semiconductor device layout...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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07043711

ABSTRACT:
A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device is disclosed. The method allows a customer to create a partial layout of the semiconductor device based on a first set of rules, and then allows a manufacturer to generate a more complete layout of the semiconductor device based on the partial layout and the second set of rules.

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“Optical Proximity Correction”, web page.
Geiger, Randall L.,VLSI Design Techniques for Analog and Digital Circuits, pp. 56-59.
“Mosis Layer Map for TSMC35—SIL—and TSMC35—P2” web page.
“MOSIS Scalable CMOS (SCMOS) Design Rules (Revision 8.0)” web page.

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