Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-03-08
2005-03-08
Baderman, Scott (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S301000
Reexamination Certificate
active
06865693
ABSTRACT:
A debugging circuit capable of debugging a plurality of possible microprocessors, and a switch for use in the same. The debugging circuit includes a debugging port, a plurality of microprocessor sockets each adapted to receive a microprocessor, and a plurality of switches corresponding to a respective microprocessor socket. The plurality of microprocessor sockets are adapted to form a serial signal path, and each of the switches is capable of automatically detecting whether a microprocessor is present in the corresponding microprocessor socket. If a microprocessor is present, the switch is automatically configured to include the microprocessor within the signal path, and if the microprocessor is not present, the switch is automatically configured so that the signal path bypasses that microprocessor socket.
REFERENCES:
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patent: 5615331 (1997-03-01), Toorians et al.
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patent: 5852617 (1998-12-01), Mote, Jr.
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U.S. Appl. No. 09/704,626, titled “System and Method for Processor Bus Termination” by inventors James H. Singer and Sandor Farkas, filed Nov. 2, 2000.
Baderman Scott
Baker & Botts L.L.P.
Dell Products L.P.
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