System and method for data transfer between multiple processors

Details System and method for data transfer between multiple processors System and method for data transfer between multiple processors

2004-09-15

2008-07-22

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S119000, C711S120000, C711S146000, C711S148000, C711S149000

Reexamination Certificate

active

07404044

ABSTRACT:
A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably coupled to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In an embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme.

REFERENCES:
patent: 2004/0039880 (2004-02-01), Pentkovski et al.
patent: 2005/0160235 (2005-07-01), Steely et al.

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