Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-02
2005-08-02
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06925622
ABSTRACT:
A clock network synthesis method and apparatus corrects for clock skew and impedance differences. A method includes identifying clock networks having more active elements as compared to other clock networks of a plurality of clock networks, for those identified clock networks, identifying a pattern of active elements therein as transversed by a clock signal, and for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements transversed by the clock signal match those transversed in the identified clock networks. A method for preventing clock skew and impedance differences includes performing a clock balancing, identifying each related node across a sub-network, identifying each input driven via the identified related nodes, and adding one or more active elements to one or more nodes until each element in the identified related nodes drives a same number of inputs.
REFERENCES:
patent: 6536024 (2003-03-01), Hathaway
patent: 6625787 (2003-09-01), Baxter et al.
patent: 6637014 (2003-10-01), Casavant
patent: 6701507 (2004-03-01), Srinivasan
Do Thuan
Fortkort John A.
Fortkort Grether & Kelton LLP
Freescale Semiconductor Inc.
Kelton Margaret M.
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