Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-04-30
2004-09-14
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S768000, C714S773000
Reexamination Certificate
active
06792567
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to reducing errors in memory devices, and particularly to reducing soft errors in dynamic memory devices using error checking and correcting circuitry.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices are known to store a data bit value in a memory cell by maintaining a charge stored on a capacitor. This technique for maintaining data makes DRAM devices more susceptible to soft errors caused by alpha particle hits or weak memory cells. Soft errors are seen to discharge the charge stored in a memory cell capacitor, resulting in a logic high data bit becoming a logic low data bit.
In applications where data integrity is critically important, systems including DRAMs often utilize error checking and correcting (ECC) capability. ECC has been previously implemented in software executed by a memory controller associated with the DRAM device, and in hardware within the DRAM device itself. With respect to the latter, ECC capability is implemented as part of the row access cycle of a memory access operation or as part of the column access cycle thereof. When ECC capability is implemented in the row access cycle, ECC operates on an entire row of data, such as 1024 bits, which improves efficiency with reduced silicon area. ECC operations in row access cycles are substantially hidden from normal memory read/write operations because of the prolonged time period for the row access cycle.
When ECC capability is implemented in the column access cycle of a memory read/write operation, efficiency is reduced due to the ECC operations being performed on shorter data words. The size of the ECC circuitry is less than when performed during the row access cycle. More importantly, the ECC circuitry and/or operation is in the critical path of a memory access operation. A 3 ns delay overhead for performing an ECC operation, for example, would render ineffective a DRAM device having a required 5 ns access time. However, the need to reduce cost and/or silicon size results in a general preference for performing error checking and correcting during the column access cycle of a memory read/write operation.
Based upon the foregoing, there is a need for more efficiently reducing soft errors in a memory device, such as a DRAM device, with relatively little impact on silicon space and DRAM performance.
SUMMARY OF THE INVENTION
Embodiments of the present invention overcome shortcomings in prior memory devices and satisfy a significant need for a memory device having reduced susceptibility to soft errors. In accordance with an exemplary embodiment, a memory device includes a dual port memory having a first port for externally initiated memory access operations and a second port for performing ECC operations. The dual port memory is capable of performing memory operations on words, with each word including data bits and error code bits. An error module, coupled to the second port of the dual port memory, performs an error checking operation on words read from the dual port memory via the second port thereof. An error controller, coupled to the error module, controls the error module to detect errors in each word sequentially read from the dual port memory via the second port thereof. The error checking is performed substantially in parallel with externally-initiated memory access operations performed using the first port of the dual port memory. The error module may also generate a corrected word based upon a word that is detected as having a correctable error. The error controller may replace the word having the correctable error with the corrected word in the dual port memory.
An operation of the memory device, in accordance with an exemplary embodiment of the present invention, includes performing externally-initiated memory access operations on a memory device via the first port thereof, and performing, substantially in parallel with performing externally-initiated memory access operations, error checking and correcting operations on words stored in the memory device via a second port thereof.
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European Search Report, EP 02252819, dated Feb. 18, 2004.
Dildine R. Stephen
STMicroelectronics Inc.
Szuwalski Andre
LandOfFree
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