Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-06-03
2008-06-03
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07383393
ABSTRACT:
A first prefetch engine from a first plurality of prefetch engines is allocated to a first load instruction in response to a buffer miss of an iteration of the first load instruction in a program stream. The first plurality of prefetch engines include prefetch engines for prefetching data from memory to a buffer based on a predicted stride. A second prefetch engine from a second plurality of prefetch engines is allocated to the first load instruction in response to the buffer miss. The second plurality of prefetch engines include prefetch engines for prefetching data from memory to the buffer based on an instruction loop representative of a sequence of instructions that affect an address value associated with an allocated load instruction. One of the first or second prefetch engines is deallocated if the other prefetch engine achieves a prefetch performance greater than a first threshold value.
REFERENCES:
patent: 2003/0110366 (2003-06-01), Wu et al.
patent: 2004/0054990 (2004-03-01), Liao et al.
Collins et al., Speculative Precomputation: Long-range Prefetching of Delinquent Loads, 28th International Symposium on Computer Architecture, 2001.
Wang et al., Speculative Precomputation: Exploring the Use of Multithreading for Latency, Intel Technology Journal, Issue 1- vol. 6, 2002.
Collins et al., Dynamic Speculative Precomputation, 34th Annual International Symposium on Computer Architecture, 2001.
Cuhna, Speculative Precomputation, 5th Internal Conference on Computer Architecture, 2004.
Sherwood, et al., Predictor-Directed Stream Buffers, Proceedings of the 33th International Symposium on Microarchitecture, 2000.
Brown et al., Speculative Precomputation on Chip Multiprocessors, 6th Workshop on Multithreaded Execution, Architecture, and Compilation, 2002.
Al Sukhni Hassan F.
Holt James C.
Bragdon Reginald
Freescale Semiconductor Inc.
Ruiz Aracelis
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