System and method for cooperative execution of multiple...

Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition

Reexamination Certificate

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Reexamination Certificate

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10256864

ABSTRACT:
A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction. A subsequent conditional execution instruction may then specify a condition in the second flag register in order to conditionally execute target instructions based on a previously existing condition.

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“The PowerPC Architecture: A specification for a new family of RISC processors.” IBM, 2nd ed., May 1994, pp. 19-22, 32-40, 57, 384-388.—Author(s)—n/a.

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