Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
2007-11-20
2007-11-20
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
Reexamination Certificate
active
10256864
ABSTRACT:
A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction. A subsequent conditional execution instruction may then specify a condition in the second flag register in order to conditionally execute target instructions based on a previously existing condition.
REFERENCES:
patent: 4969091 (1990-11-01), Muller
patent: 5193157 (1993-03-01), Barbour et al.
patent: 5768500 (1998-06-01), Agrawal et al.
patent: 5951696 (1999-09-01), Naaseh et al.
patent: 5974240 (1999-10-01), Chan
patent: 6016543 (2000-01-01), Suzuki et al.
patent: 6047369 (2000-04-01), Colwell et al.
patent: 6065115 (2000-05-01), Sharangpani et al.
patent: 6108766 (2000-08-01), Hahn et al.
patent: 6374346 (2002-04-01), Seshan et al.
patent: 6574728 (2003-06-01), Chayut
patent: 6662294 (2003-12-01), Kahle et al.
patent: 6760831 (2004-07-01), Drabenstott et al.
patent: 2002/0199090 (2002-12-01), Wilson
patent: 0 130 381 (1985-01-01), None
“The PowerPC Architecture: A specification for a new family of RISC processors.” IBM, 2nd ed., May 1994, pp. 19-22, 32-40, 57, 384-388.—Author(s)—n/a.
Kalluri Seshagiri P.
Krolnik Adam C.
Trombetta Ramon C.
Chan Eddie
Petranek Jacob
VeriSilicon Holdings (Cayman Islands) Co. Ltd.
LandOfFree
System and method for cooperative execution of multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for cooperative execution of multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for cooperative execution of multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3881447