System and method for controlling timing of output signals

Details System and method for controlling timing of output signals System and method for controlling timing of output signals

2008-05-16

2010-12-21

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C327S261000, C327S291000

Reexamination Certificate

active

07855928

ABSTRACT:
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.

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