Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-10-24
2003-12-23
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S057000, C370S470000, C709S250000
Reexamination Certificate
active
06668290
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to data communication in computer systems, and more particularly to a system and method implemented in connection with a FIFO frame buffer for preventing overreading of data from the buffer.
BACKGROUND OF THE INVENTION
Advances in computer technologies have resulted in increased processing power and the use of increasingly data-intensive computer applications. Accordingly, there is a greater need for high-performance data links and networking applications to support the interconnected computers, storage devices, displays, I/O devices, and other peripherals.
Traditional data links between interconnected devices often cannot operate at sufficiently high speeds to support current systems. Consequently, Fibre Channel communication links, which provide very high-speed, low-latency, full-duplex data communications, are increasingly being used to meet the data transfer requirements of these systems.
Fibre channel systems provide a transport mechanism in which frames are used to transfer data. The frames contain the data to be transmitted, as well as the addresses of the source and destination ports, and link control-information. Each frame includes delimiters which identify the beginning and end of the frame and thereby allow frames to be written and read individually.
While the frames are well defined and easily identifiable as a result of the delimiters, the speed of the data transfer may be too great for the read or write logic to respond to the delimiters and stop reading or writing at precisely the end of the frame. This may cause a number of problems. For example, if the frame is stored in a FIFO and is destructively read out of the FIFO, data beyond the end of the frame may be read out and lost. (Once the data is read out of the FIFO, it cannot be returned to the FIFO—if it cannot be transmitted to another device or stored in another memory, it is lost.)
SUMMARY OF THE INVENTION
One or more of the problems outlined above may be solved by the various embodiments of the invention which, broadly speaking, comprises a system and method for reading a stream of high-speed data without interrupting the data or reading beyond the end of a desired frame of data.
In one embodiment, the system comprises a receive buffer which is coupled to associated write logic and read logic. A data stream is delivered to the system, wherein the data stream comprises a plurality of frames. Each frame comprises a plurality of words, wherein a first word is identified by a start-of-frame (SOF) delimiter and a last word is identified by an end-of-frame (EOF) delimiter. The buffer is configured to be accessed by the read and write logic in a first-in-first-out fashion. In one embodiment, the write logic includes two serial pipeline stages through which received words pass. The word in the first stage is examined to determine whether it comprises an EOF delimiter. If it is an EOF delimiter, the write logic sets an early-end-of-frame (early_EOF) bit in the word which is in the second pipeline stage. As a result, the early_EOF bit is set in the penultimate, or next-to-last, word in each frame. When it is desired to read a frame out of the buffer, the read logic is configured to start reading words out of the buffer. As each word is read out, it is examined by the read logic to determine whether the corresponding early_EOF bit is set. If this bit is not set, the read logic does not anticipate the end of the frame and continues to read successive words out of the buffer. When the read logic reads a word out of the buffer and the early_EOF bit is set in that word, the read logic anticipates the end of the frame and prepares to stop reading after the next word (which is the last word in the frame.) The system thereby provides sufficient setup time for the read logic to stop reading words out of the buffer before reaching the next frame.
In one embodiment, the method comprises modifying the frames of data which are written into a receive buffer to indicate the next-to-last word in each frame. Each frame comprises a plurality of words, wherein a first word is an SOF delimiter and a last word is an EOF delimiter. As the words of a frame are received, they are examined to determine whether each is the last word in the frame, as indicated by the EOF delimiter. Each word is written into a receive buffer, along with an early_EOF bit which indicates whether the word is the next-to-last word in the frame. If the early_EOF bit is set, the corresponding word is the next-to-last word in the frame. The frames are read out of the buffer in the order in which they were written to the buffer (first-in-first-out.) When it is desired to read a frame out of the buffer, a read operation is initiated. As each word of a frame is read out of the buffer, the word is examined to determine whether its early_EOF bit is set or cleared. If the early_EOF bit is cleared, successive words are read out of the buffer until a word having its early_EOF bit set is encountered. If the early_EOF bit is set, the next word is read and then the read operation is terminated.
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patent: 5691984 (1997-11-01), Gardner et al.
patent: 5872920 (1999-02-01), Hausman et al.
patent: 6105086 (2000-08-01), Doolittle et al.
patent: 6151307 (2000-11-01), Gauthier et al.
patent: 0 412 267 (1991-02-01), None
Crossroads Systems Inc.
Gray Cary Ware & Freidenrich LLP
Huynh Kim
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