Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
1999-08-03
2002-02-19
Le, Hoa Van (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C438S017000
Reexamination Certificate
active
06348289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to systems and methods for controlling polysilicon feature critical dimension during processing.
2. Description of the Related Art
The information described below is not admitted to be prior art by virtue of its inclusion in this Background section.
The desire to reduce contamination in semiconductor fabrication processes is never-ending. In such processes, contamination can arise in many forms, including as particulates, organic residues, and inorganic residues. Even in trace amounts, the presence of contaminants on a wafer surface can produce defects in semiconductor devices formed on the wafer. These defects can prove highly problematic; in some cases, just one very small defect can render a circuit inoperable. Consequently, it is generally desirable to reduce the amount of contaminants on a wafer surface as much as possible.
Because eliminating contamination is so important, cleaning processes play a large role in semiconductor fabrication processes. A variety of cleaning processes may be used in a semiconductor fabrication sequence. The particular type of process used often will vary with the type of contaminants to be removed, as well as with other process considerations. Most semiconductor cleaning processes, however, fall into the category of wet cleaning. Generally speaking, wet cleaning processes are processes in which liquid chemical solutions are used to clean contaminants from a wafer surface. Cleaning may be performed by immersing the wafer in the cleaning solution, or by other techniques such as spraying a cleaning solution onto a rotating wafer. After cleaning is complete, the wafer is typically rinsed and dried.
One of the most important segments of semiconductor processing is the fabrication of metal-oxide-semiconductor (MOS) circuits. Cleaning processes play a large role in MOS circuit manufacturing, particularly in one of the most fundamental steps of such processes: the formation of the polysilicon transistor gates. While there are numerous methods of forming an MOS transistor gate, a typical process may begin by forming a gate oxide upon the surface of a single-crystal silicon wafer. A layer of polysilicon is then formed above the gate oxide layer. Subsequently, an anti-reflective coating (ARC) layer is formed above the polysilicon layer. The ARC layer is typically a layer of dielectric material, such as silicon oxynitride, upon which resist will be deposited. The ARC layer serves to minimize reflections during resist exposure. Resist may then be spun on, exposed, and developed, leaving a pattern corresponding to the desired pattern of the polysilicon gates. An anisotropic etch process, such as reactive ion etching, may then be used to remove polysilicon (as well as directly overlying portions of the ARC layer) not protected by the developed resist pattern. After etching is complete, the remaining resist and ARC waiters are stripped. Etch processes often produce a substantial amount of contamination, and so after etching is complete the wafer may be rinsed, and then immersed in a cleaning solution. Following immersion, the wafer may be rinsed again and dried.
An important objective of the gate formation process is to produce a gate having a particular critical dimension. The critical dimension of a feature, such as a gate, is essentially the width of that feature. Because of the exacting nature of semiconductor devices, it is desirable to maintain the critical dimension (CD) of features within design tolerances. For example, in self-aligned structures, the channel length is established by the gate width. As the channel length influences, among other things, the speed of a transistor, control of the gate CD is important. Fortunately, current photolithographic processes are capable of producing a gate having a post-gate etch critical dimension (PG CD) relatively close to a desired value.
Unfortunately, the processes that follow gate etch can significantly reduce the gate critical dimension from the PG CD. For example, an ARC layer composed of silicon oxynitride may typically be stripped using a solution of reflux boiled phosphoric acid. While effective at removing silicon oxynitride, the phosphoric acid solution can etch the polysilicon of which the gate is composed. Furthermore, subsequently employed cleaning processes may also etch polysilicon. As such solutions typically remove silicon from a gate at substantially equal rates on both sides of the gate, the total CD reduction will be about twice the polysilicon etch rate of the solutions. Thus, the total CD reduction resulting from post-gate etch processes can be significant, e.g., 5-10 nm or more. Consequently, the final CD of a polysilicon gate after post-gate etch processing is complete can be significantly less than PG CD.
Losses in gate CD resulting from post-gate etch processing can be partially compensated for, however. As stated above, current photolithographic processes allow for significant control of gate critical dimension. Consequently, the PG CD may be adjusted in accordance with the expected CD reduction that will result from post-gate etch processing. Thus, if one could accurately predict the amount of gate CD that will be lost to post-gate etch processing, a polysilicon gate could be produced with a final CD (i.e., CD after post-gate etch processing is complete) that is very close to a goal CD.
As might be expected, however, the CD loss from post-gate etch processing can be difficult to predict. The extent to which such processes etch polysilicon and other silicon-bearing surfaces is dependent on the relative values of the etch-rate effective attributes of the solutions, such as concentration or temperature. In semiconductor processing, however, chemical solutions are often repeatedly used on numerous lots of wafers, and values of the etch-rate effective attributes of the solutions tend to vary with time. In addition, the amount of variation can be further dependent on variables that are not always constant from run-to-run. As such, attempts to precisely estimate the CD loss from post-gate etch processing can be easily frustrated.
An example of the above may be seen in a cleaning process commonly used to remove contaminants arising during the poly gate formation process, the SC1 clean. The SC1 clean is a component process of the traditional RCA cleaning process, and is especially useful in the removal of organic and metallic contaminants. SC1 solutions are solutions of water, hydrogen peroxide (H
2
O
2
), and ammonium hydroxide (NH
4
OH) (in order of decreasing concentration), which are typically maintained between 60 and 85° C. during use. In addition, SC1 solutions may include other chemicals, such as chelating agents used to bind up metallic ions present in the solution. SC1 solutions may etch polysilicon by a continual oxidation-reduction process of forming an oxide layer and removing the oxide layer.
The rate at which an SC1 solution etches polysilicon depends on etch-rate effective parameters of the solution such as the solution temperature and the respective concentrations of hydrogen peroxide and ammonium hydroxide within the solution. Higher relative concentrations of ammonium hydroxide to hydrogen peroxide within a SC1 solution can result in elevated silicon etch rates during cleaning.
Over time, the etch-rate effective attributes of an SC1 solution may vary significantly. For example, as an SC1 solution is repeatedly used, hydrogen peroxide within the solution may decompose. Such decomposition can occur, for example, as the result of impurities accumulating within the solution or the solution temperature rising too far above certain levels. As the concentration of hydrogen peroxide within a SC1 solution decreases, the polysilicon etch rate of that solution will tend to correspondingly increase. Furthermore, the variables that affect hydrogen peroxide decomposition are often inconstant from run-to-run, making precise estimates of the polysilicon etch
Campbell W. Jarrett
Couteau Terri A.
Toprac Anthony
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Le Hoa Van
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