System and method for controlling data transfer for data...

Details System and method for controlling data transfer for data... System and method for controlling data transfer for data...

2006-04-11

2006-04-11

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S001000, C710S016000, C710S031000, C710S071000, C712S025000, C712S027000, C375S145000, C375S240210, C341S100000

Reexamination Certificate

active

07028108

ABSTRACT:
A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n−1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n−1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

REFERENCES:
patent: 6687303 (2004-02-01), Ishihara

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