Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-12-11
2007-12-11
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
10879255
ABSTRACT:
In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
REFERENCES:
patent: 7058782 (2006-06-01), Henderson et al.
patent: 7096407 (2006-08-01), Olarig
S. Kaneda and E. Fujiwara; “Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems,” IEEE Transactions on Computers, vol. C-31, No. 7, Jul. 1982.
Gostin Gary
Nerl John A.
Pomaranski Ken
Soper David
Walton Andrew
Chase Shelly A
Hewlett--Packard Development Company, L.P.
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