Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2005-04-26
2005-04-26
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S322000, C327S175000
Reexamination Certificate
active
06886106
ABSTRACT:
A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
REFERENCES:
patent: 6515530 (2003-02-01), Boerstler et al.
patent: 6566918 (2003-05-01), Nguyen
patent: 6639441 (2003-10-01), Ono et al.
patent: 6781419 (2004-08-01), Harrison
Nelson Victor P. et al., Digital Logic Circuit Analysis and Design, 1995, Prentice-Hall Inc., pp. 268-277.
Brock Bishop Chapman
Carpenter Gary Dale
Caswell Amanda Christine
MacDonald Eric William
Rubidoux Timothy Joe
Butler Dennis M.
Carr LLP
Carwell Robert M.
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