Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2011-07-12
2011-07-12
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S154000
Reexamination Certificate
active
07979666
ABSTRACT:
A system and method for context-independent coding using frequency-based mapping schemes, sequence-based mapping schemes, memory trace-based mapping schemes, and/or transition statistics-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using the current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. A single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.1% degradation in performance.
REFERENCES:
patent: 6696993 (2004-02-01), Karczewicz
patent: 2003/0048208 (2003-03-01), Karczewicz
patent: 2007/0290901 (2007-12-01), Hekstra et al.
patent: 2008/0219575 (2008-09-01), Wittenstein
patent: 2008/0235560 (2008-09-01), Colmer et al.
Rixner, “Memory Controller Optimizations for Web Servers,” Proceedings of the 37th Int'l Symposium on Microarchitecture (MICTO-37'04).
Delaluz, V., Kandemir, M., Vijaykrishnan, N., Sivasubramaniam, A., Irwin, M. “DRAM energy management using software and hardware directed power mode control,” Proceedings of the International Symposium on High-Performance Computer Architecture (2001).
Fan, X., Ellis, C., Lebeck, A., “Memory controller policies for dram power management,” Proceedings of the International Symposium on Low Power Electronics and Design (2001).
Sotiriados, P., Chandrakasan, A., “Low Power Bus coding Techniques Considering Inter-wire Cpacitances,” IEEE 2000 Custom Integrated Circuits Conference (2000).
Kulkarni, C., Catthoor, F., DeMan, H., “Code transformations for low power caching in embedded multimedia processors,” Proceedings of the International Parallel Processing Symposium (1998).
Kulkarni, C., Miranda, M., Ghez, C., Catthoor, F., Man, H.D., “Cache conscious data layout organization for embedded multimedia applications,” Proceedings of the Design and Test in Europe Conference. (2001).
Panda, P.R., Dutt, N.D., Nicolau, A., “On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems,” ACM Transactions on Design Automation of Electronic Systems 5 (2000) 682-704.
Benini, L., Macii, A., Poncino, M., Scarsi, R., “Architectures and synthesis algorithms for power-efficient bus interfaces,” IEEE Trans. Computer-aided Design, vol. 19, No. 9, pp. 969-980 (2000).
Ramprasad, S., Shanbag, N.R., Hajj, I.N., “A coding framework for low power address and data buses,” IEEE Transactions on VLSI Systems vol. 7 pp. 212-221 (Jun. 1999).
Deogun, H., Rao, R., Sylvester, D., and Blaauw, D., “Leakage-and Crosstalk-Aware Bus encoding for Total Power Reduction,” DAC 2004, Jun. 7-11, 2004, San Diego, CA (2004).
Sotiriadis, P., Tarokh, V., Chandrakasan, A.P., “Energy reduction in VLSI computation modules: An information-theoretic approach,” IEEE Transactions on Information Theory, vol. 49, pp. 790-808.
Stan, M.R. and Burleson, W.P., “Low-power encodings for global communication in CMOS VLSI,” IEEE Transactions on VLSI Systems, vol. 5, No. 4 (1997).
Stan, M.R. and Burleson, W.P., “Bus invert coding for low power I/O,” IEEE Transactions on VLSI Systems vol. 3, No. 1 pp. 49-58 (1995).
Benini, L., DeMicheli, G., Macii, E., Sciuto, D. and Silvano, C., “Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems,” Proceedings of the Great Lakes Symposium on VLSI, pp. 77-82 (1997).
Musoll, E., Lang, T. and Cortadella, J., “Exploiting locality of memory references to reduce the address bus energy,” Proceedings of the International Symposium on Low Power Electronics Design, pp. 202-207 (1997).
Yang, J., Gupta, R. and Zhang, C., “Frequent value encoding for low power data buses,” ACM Trans. Des. Automation Electronic Systems, vol. 9, 354-384 (2004).
M. R. Guthaus et al., “MiBench: A free, commercially representative embedded benchmark suite,” in IEEE Workshop on Workload Characterization, 2001.
M. Q. Do et al., “Parameterizable architecture-level SRAM power model using circuit-simulation backend for leakage calibration,” in Proc. Intl. Symposium Quality Electronic Design, pp. 557-563, 2006.
Suresh, D., Agrawal, B., and Najjar, W., “A Tunable Bus Encoder for Off-Chip Buses,” ISLPED '05, Aug. 8-10, 2005, San Diego, CA (2005).
Austin, T., Larson, E., Ernst, D.: SimpleScalar: An infrastructure for computer system modeling. IEEE Computer (2002).
Clark, L.T., Hoffman, E.J., Miller, J., Biyani, M., Liao, Y., Strazdus, S., Morrow, M., Velarde, K.E., mark A. Yarch: An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE Journal of Solid-state Circuits 36 (2001) 1599-1608.
Yang, J., Gupta, R., “Frequent Value Locality and its Applications,” ACM Transactions on Embedded Computing Systems, vol. 1, No. 1, Nov. 2002, pp. 79-105.
Wen, V., Whitney, M., Patel, Y. and Kubiatowicz, J. “Exploiting Prediction to Reduce Power on Buses,”.
Basu, K., Choudhary, A., Pisharath, J., and Kandemir, M., “Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses,” Proceedings of the 35th Annual IEEE/ACM Int'l Symposium on Microarchitecture (MICRO-35)(2002).
Benini, L., Bruni, D., Macii, A., and Macii, E., “Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors,” Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (2002).
Lekatsas, H., Henkel, J., and Wolf, W., “Code Compression for Los Power Embedded System Design,” DAC 2000, Los Angeles, CA (2000).
Benini, L., Macii, A., Macii, E., and Poncino, M., “Selective Instruction Compression for Memory Energy Reduction in Embedded Systems,” ISLPED99, San Diego, CA (1999).
Wolfe, A and Chanin, A., “Executing Compressed Programs on an Embedded RISC Architecture,” IEEE (1992).
Liao, S., Devadas, S. and Keutzer, K., “Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques,” IEEE (1998).
Choudhury Mihir R.
Mohanram Kartik
Rixner Scott
24IP Law Group
DeWitt Timothy R.
Elmore Reba I.
William Marsh Rice University
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