Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-02-16
2002-11-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06481002
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-39240 filed on Feb. 17, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a CAD tool and compressing method for compressing and preparing LSI mask writing data. More specifically, the invention relates to an LSI mask writing data compressing system and method for compressing flat design data to prepare writing data having a high compressibility in order to supply the prepared writing data to a mask lithography system of a vector scan system. The invention also relates to a recording medium in which a computer program for executing the LSI mask writing data compressing method has been recorded.
2. Related Background Art
The capacity of LSI mask writing data for use in a process for producing large scale integrated circuits is increasing with the increase of the scale of products, and recently, reaches several giga bytes. As a method for compressing writing data, the repeated expression of layout patterns is usually used. However, even if the compressing method using only the repeated expression of layout patterns is carried out, there is a limit to compressibility, and it is not possible to sufficiently cope with the increase of the scale of products in the present circumstances.
LSI mask lithography systems are divided broadly into raster scan systems and vector scan systems. The vector scan systems are easy to realize precise writing and high throughput, and are being mainly used for carrying out very large scale, precise LSC mask wiring.
Writing data in recent vector scan systems are expressed by a format having a hierarchical structure for the purpose of preparing writing data of a high compressibility for VLSI products.
LSI design data originally have a hierarchical structure, and are relatively easy to prepare mask writing data of a high compressibility using a hierarchical expression if direct mask writing data are prepared by converting the design data without processing the design data, and such preparation is actually in some cases.
However, since a complicated data processing including the logical operation of layout patterns, the dimensional correction of layout patterns, the proximity effect correction and so forth is actually carried out when design data are converted into mask writing data, the hierarchical structure of the design data can not been maintained, so that a part of the design data are usually flattened. In the worst case, the design data may have a completely flat structure.
Conventionally, when such flat design data having no hierarchical structure are handled, the repeated expression of layout patterns is widely used as the mask writing data compressing method. However, even if the compressing method using only the repeated expression of layout patterns is carried out, there is a limit to the compressibility of data. Therefore, in the case of the mask writing data of VLSI products, the size of data reaches several giga bytes.
For that reason, a mass of data are handled, so that there are problems in that it takes a lot of time to process mask writing data and that large-capacity working storage files are required for processing data on the side of a mask lithography system.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide an LSI mask writing data compressing system and method for preparing mask writing data having a very high compressibility using the hierarchical expression of mask writing data when the mask writing data are prepared from LSI design data having a flat structure having no hierarchical structure.
According to an LSI mask writing data compressing system of the present invention, there is provided an LSI mask writing data compressing system comprising:
an individual layout pattern one-dimensional array generating unit for generating first-coordinate-axial one-dimensional arrays for each individual layout pattern and second-coordinate-axial one-dimensional arrays for each individual layout pattern by using layout pattern data of unit section regions of LSI design data, which comprise a plurality of unit section regions and which correspond to the unit section regions of LSI mask writing data to be compressed, from layout patterns of the unit section regions, and for setting layout pattern data of the residual layout patterns as random layout pattern data, each of the first-coordinate-axial one-dimensional arrays for each individual layout pattern being formed by repeatedly arranging individual layout patterns having the same shape on an LSI mask writing plane at regular intervals in the direction of a first coordinate axis, each of the second-coordinate-axial one-dimensional arrays for each individual layout pattern being formed by repeatedly arranging individual layout patterns having the same shape on the LSI mask writing plane at regular intervals in the direction of a second coordinate axis perpendicular to the first coordinate axis;
an individual layout pattern two-dimensional array generating unit for generating two-dimensional arrays for each individual layout pattern from selected first-coordinate-axial one-dimensional arrays for each individual layout pattern, which are selected from the first-coordinate-axial one-dimensional arrays for each individual layout pattern, each of the selected first-coordinate-axial one-dimensional arrays for each individual layout pattern including the same number of the individual layout patterns having the same shape arranged at the same regular intervals in the direction of the first coordinate axis, each of the two-dimensional arrays for each individual layout pattern being formed by repeatedly arranging the selected first-coordinate-axial one-dimensional arrays for each individual layout pattern on the LSI mask writing plane at regular intervals in the direction of the second coordinate axis;
a multiple layout pattern block array generating unit for generating a first-coordinate-axial block array of multiple layout patterns from the residual first-coordinate-axial one-dimensional arrays for each individual layout pattern other than the selected first-coordinate-axial one-dimensional arrays for each individual layout pattern which have constituted any one of the two-dimensional arrays for each individual layout pattern, the first-coordinate-axial block array of multiple layout patterns being formed by grouping the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of the first coordinate axis regardless of the shape of individual layout patterns included in the first-coordinate-axial block array of multiple layout patterns, for generating a second-coordinate-axial block array of multiple layout patterns from the residual second-coordinate-axial one-dimensional arrays for each individual layout pattern other than the selected second-coordinate-axial one-dimensional arrays for each individual layout pattern which have constituted any one of the two-dimensional arrays for each individual layout pattern, the second-coordinate-axial block array of multiple layout patterns being formed by grouping the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of the second coordinate axis regardless of the shape of individual layout patterns included in the second-coordinate-axial block array of multiple layout patterns, and for generating a two-dimensional block array of multiple layout patterns from the two-dimensional arrays for each individual layout pattern, the two-dimensional block array of multiple layout patterns being formed by grouping the same number of individual layout patterns of the two-dimensional arrays of individual layout patterns repeatedly arranged at the same regular inte
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Siek Vuthe
Tat Binh
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