Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-02-21
2009-02-17
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S133000, C711S141000, C710S310000
Reexamination Certificate
active
07493446
ABSTRACT:
A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
REFERENCES:
patent: 5023776 (1991-06-01), Gregor
patent: 6105112 (2000-08-01), Arimilli et al.
patent: 6173371 (2001-01-01), Arimilli et al.
patent: 6557084 (2003-04-01), Freerksen et al.
patent: 6678799 (2004-01-01), Ang
patent: 6772298 (2004-08-01), Khare et al.
patent: 6976130 (2005-12-01), Chi
patent: 7089364 (2006-08-01), Arimilli et al.
patent: 7188216 (2007-03-01), Rajkumar et al.
patent: 2001/0052053 (2001-12-01), Nemirovsky et al.
patent: 2004/0064643 (2004-04-01), Jamil et al.
patent: 2005/0251660 (2005-11-01), Bell et al.
Eberhard et al., “Storage Access Mechanism for Vector Operands”, Dec. 1994, IBM Technical Disclosure Bulletin, vol. 37, No. 12, pp. 629-632.
Arimilli Ravi Kumar
Guthrie Guy Lynn
Shen Hugh
Williams Derek Edward
Dillon & Yudell LLP
International Business Machines - Corporation
Salys Casimer K.
Savla Arpan
Shah Sanjiv
LandOfFree
System and method for completing full updates to entire... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for completing full updates to entire..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for completing full updates to entire... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4101489