Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-24
2002-05-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06385758
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a graphic layout compaction system and a graphic layout compaction method.
An automatic layout system is utilized for designing a layout of a large-scale semiconductor integrated circuit or a printed-circuit board. The large-scale semiconductor integrated circuit includes a lot of semiconductor cells. The printed-circuit board mounts a lot of parts thereon. The semiconductor cells may be merely referred to cells. The semiconductor cells and the parts are collectively called components in the present specification. Although each component has at least one terminal which is called a component terminal, the component terminal may be called the component. In addition, in the automatic layout system of the type, various compaction techniques for moving components with the components linked are already proposed.
A conventional graphic compaction system is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 9-204461 (204461/1997) (Publication 1). In this system, the layout of a plurality of components is compacted with relative position relationship of the components held. However, this graphic compaction system is disadvantageous in that it is impossible to compact a pattern having routes or wires between component terminals. This is because this graphic compaction system places or arranges only the parts (the components) on a printed-circuit board in a stage prior to routing or wiring between terminals (the component terminals) of the parts and then compacts its placement or arrangement.
Another conventional graphic compaction system is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 1-279373 (279373/1989) (Publication 2). The graphic compaction system compacts semiconductor cells (the components) and routes or wires in a stage after routing or wiring between terminals (the component terminals) of cells on designing of an integrated circuit.
As disclosed in Japanese Unexamined Patent Publications (JP-A) Nos. 62-78681 (78681/1987) (Publication 3) and 63-214880 (214380/1988) (Publication 4), compaction of the routes or wires together with semiconductor cells or parts (components) frequently adopts a scheme using a constraint graph. For the compaction using the constraint graph, proposal is made of a jog insertion compaction technique by W. Yanamoto et al in their articles “A Chip Compaction Method on Constraint Graph and the Experimental Result”, Technical Report of IEICE VLD91-43, pp. 41—48, 1991 (Article 1), “A Chip Spacing Method for layouts with Design-Rule Violations”, Technical Report of IEICE VLD91-120, pp. 37-44, Feb. 7, 1992 (Article 2), and “A Chip Spacer with Automatic
45
° Diagonal Wiring Generation”, Technical Report of IEICE VID91-123, pp. 17-24, 1992 (Article 3). The jog insertion compaction technique modifies structure of the constraint graph by inserting a bend part called “jog” in the routing or wiring to thereby enable to reduce an area of the layout and to correct places with design-rule violations.
Referring to
FIG. 1
, a conventional layout compaction system comprises a cell placement processing unit (cell arrangement processing unit)
710
, an inter-cell routing processing unit
720
, a longest route searching unit
730
, a layout enlarging unit
740
, a layout correction designating unit
750
, an automatic layout compressing unit (compaction unit)
760
, a layout data memory
770
, and a layout result display unit
780
.
The conventional layout compaction system having such structure operates in a following manner.
The cell placement processing unit
710
carries out processing of placement or arrangement for cells as known in the art and stores cell layout data indicative of a layout of the cells in the layout data memory
770
.
As known in the art, the inter-cell routing processing unit
720
carries out processing of routing or wiring between cells and stores routing layout data (wiring layout data) indicative of a layout of the routing or the wiring in the data Emory
770
.
The longest route searching unit
730
searches a series of graphic elements having the longest route in the layout stored in the layout data memory
770
in order to compact a layout of each cell and the routing or wiring on an LSI chip into a smaller area and displays it in the layout data memory
770
and displays the longest route in the layout result display
780
as depicted by oblique lines in FIG.
2
A.
As illustrated in
FIG. 2B
, the layout enlarging unit
740
inserts a space crossing the longest route of its constraint graph in the layout as shown in FIG.
2
B.
Responsive to a request from an operator, the layout correction designating unit
750
moves a particular part from the longest route of the constraint graph so as to shorten the longest route. In the example illustrated in
FIG. 2B
, the particular part is the second part from a lower end and is moved rightward.
The automatic layout compressing unit (compaction unit)
760
compacts the layout indicative of a corrected result in up and down of FIG.
2
B.
However, in a case of carrying out the compaction of the layout BO as to reduce the layout in both longitudinal and lateral directions, the conventional compactor
760
reduces the layout in two steps so as to first reduce it in one direction (e. g. the longitudinal direction) and to subsequently reduce it in another direction (e. g. the lateral direction). Therefore, when the layout is first reduced in the longitudinal direction, the cells or the components crowd in the longitudinal direction and it results in preventing reduction of placement or arrangement of the cells or the components and the layout of the routing or the wiring in the lateral direction.
In addition, those skilled in the art may hit upon a method comprising the steps of extending the Dijkstra method, of simultaneously evaluating a movable distance of the longitudinal direction and another movable distance of the lateral direction for each part or component, and of moving the parts or the components in order ascending the movable distances in its direction to place or arrange the parts or the components. However, this method is disadvantageous in that placement or arrangement of the parts or the components crowded in a particular direction selected from the longitudinal direction and the lateral direction prevents the parts or the components from subsequently moving in a direction perpendicular to the particular direction.
The reason for this defect is as follows. This conventional compaction system carries out compaction of the layout so as to first move all of the parts or the components pushed to touch a substrate end and to subsequently move all of the parts or the components pushed to touch the substrate end. Therefore, an initial result of placement or arrangement for semiconductor cells or parts is not reflected to the layout after compaction and compaction in an initial direction results in unbalancing placement or arrangement of the parts or the components. As a result, compaction of the semiconductor cells or the parts in the next direction is prevented.
In addition, to improve this defect, still another conventional graphic compaction system is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 63-181349 (181349/1988) (Publication 5). The graphic compaction system moves semiconductor cells in a symmetrical direction towards a center of the layout for a chip before routing or wiring process for an LSI, compacts the layout so that the semiconductor cells collect in a center direction of the chip, and makes routing or wiring between the semiconductor cells.
However, the compaction system described in Publication 5 divides an area of the layout about the center of the chip into four divided areas and carries out compaction in the respective divided areas. In addition, in each divided area, the compaction system carries out primary compaction of the semiconductor cells in a first direction and subsequently carries out secondary compaction of the semiconductor cells in a second direction perpendicul
Kikuchi Hideo
Shimotsu Takeshi
Do Thuan
NEC Corporation
Smith Matthew
Sughrue & Mion, PLLC
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