Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-07-07
2001-08-21
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S189050, C365S230060, C365S230080
Reexamination Certificate
active
06279071
ABSTRACT:
FIELD OF THE INVENTION
This application relates to memory devices, and in particular, to a method of providing accelerated column access to a random access memory (RAM).
BACKGROUND ART
Reference is now made to
FIG. 1
that shows a conventional system
10
for providing column access to a RAM, and
FIG. 2
that illustrates typical waveforms for a write operation. The column access system
10
comprises a column counter
12
that receives an external n-bit address signal ExtAdd<0:n> to produce a column address CA<0:n>. An external command ExtCmd defining a RAM operation is supplied to a command decoder
14
that decodes the command and produces signals required to execute it. For example, if the ExtCmd defines a write operation, the command decoder
14
produces a write enable signal WE, a global input/output equalize control signal GIOEQ, and a column decode enable signal CDE.
An address decoder
16
receives the column address CA<0:n>, together with the column decode enable signal CDE, to produce a decoded column address AYD supplied to a column select line (CSL) generator
18
. The write enable signal WE and the equalize control signal GIOEQ, together with data ZWDD, are supplied to a write driver
20
for producing a global input/output signal GIO and a complementary global input/output signal ZGIO to drive a global input/output pair GIO/ZGIO coupled to a DRAM array
22
. The global input/output pair GIO/ZGIO is used for providing data transfer during writing and reading operations. A column select line signal CSL<0:n> produced by the CSL generator
18
selects a column in the DRAM array
22
for writing the data
As shown in
FIG. 2
, a new column address CA is generated and latched in the column counter
12
at the rising edge of a clock signal CLK during a write cycle. Such latching allows the column address to be isolated from the external address ExtAdd. Thus, the external address ExtAdd can be changed without changing the generated column address CA. The write enable signal WE is activated after the column address CA is initiated.
As a result, a new CSL signal based on the new column address CA cannot be produced until the current write or read operation is completed. For example, when a precharge command is issued during a write operation, a precharge operation is delayed by the write recovery time tWR equal to the time period between the raising edge of the clock corresponding to the write operation and the raising edge of the CSL signal.
The write recovery time tWR may be greater than 1 clock cycle. In this case, a no operation command NOP must be issued between the write operation and the precharge operation.
Accordingly, it would be desirable to provide a column access system that allows the write recovery time to be reduced to eliminate a no operation cycle between a write operation and the next operation, such as a precharge operation.
Further, in the conventional column access system, the GIO/ZGIO pair is driven only when the write enable signal WE and other write control signals, such as the column decode enable signal CDE, are at a high level. Therefore, the signals WE and CDE has to be latched in the command decoder
14
to maintain them at a high level as long as a write operation occurs. Thus, in high-frequency applications, when the clock cycles are short, the write enable signal WE and the column decode enable signal CDE cannot be reset until the next clock cycle begins. As a result, the next operation is delayed.
It would be desirable to provide a column access system that allows the write control signals to be reset in the.current clock cycle to reduce a delay between operations.
DISCLOSURE OF THE INVENTION
Accordingly, one advantage of the invention is in providing a column access system that allows the time recovery time to be reduced to decrease a delay between memory operations.
Another advantage of the invention is in providing a column access system that allows write control signals to be reset in a current clock cycle to further reduce a delay between memory operations.
These and other advantages of the present invention are achieved, at least in part by providing a random access memory that comprises a column counter responsive to an external address for producing a column address. In response to an external command, a command decoder produces a column decode enable signal. An address decoder is responsive to the column address and column decode enable signal for producing a decoded column address signal used to select a column line. The address decoder has a column address latch that latches the column address to produce the decoded column address signal independently of changes in the column address supplied to the address decoder.
The address decoder may further comprise a gate circuit controlled by the column decode enable signal for passing the column address signal to the column address latch when the column decode enable signal is in an active state. The column address latch is cleared when an equalize control signal goes to an active state.
The memory may further comprise a write driver supplied with an input data signal representing data to be written in a selected memory cell. The command decoder may produce a write enable signal supplied to the write driver.
In accordance with a first embodiment of the invention, the write driver may comprise a first data latch controlled by the write enable signal for latching the input data signal. A second data latch is coupled to the first data latch for latching a first data signal supplied from the first data latch. A gate circuit is arranged between the first and second data latches for passing the first data signal to the second data latch when the write enable signal is in a first state, and for preventing the data signal from being supplied to the second data latch when the write enable signal is in a second state. The second data latch is responsive to the first data signal to produce a second data signal for driving a data output circuit of the write driver. The second data latch is cleared when the equalize control signal goes to an active state.
In accordance with a second embodiment of the invention, the write driver may comprise a write enable latch supplied with the write enable signal for producing a local write enable signal maintained at a first level until the equalize control signal goes to an active state. The local write enable signal controls a data latch for latching the input data signal. The data output circuit is driven by a data signal produced by the data latch.
In accordance with another aspect of the invention, a system for providing access to a column of a random access memory comprises:
a column counter responsive to an external address for producing a column address in a clock cycle, in which the external address is supplied, and
an address decoder responsive to the column address for producing a decoded column address signal and having a column address latch for latching the column address until an equalize control signal becomes active.
In accordance with a method of the present invention the following steps are carried out to provide access to a column of a RAM:
in response to an external address, generating a column address in a clock cycle, in which the external address is supplied, and
latching the column address until an equalize control signal becomes active.
In accordance with one embodiment of the invention, a data signal may be latched until the equalize control signal becomes active.
In accordance with another embodiment of the invention, a write enable signal may be latched until the equalize control signal becomes active.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, a
Camacho Stephen
Lao Tim
Walker Robert M.
Burns Doane Swecker & Mathis L.L.P.
Mitsubishi Electric and Electronics USA, Inc.
Portka Gary J.
Yoo Do Hyun
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